CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 26

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. When FRAMEn and REQ64n is asserted and the command bus is '0111', then a 64-bit write to memory space is indicated.
2. The Target will compare the address to the programmed space set in the memory base address register.
3. If an address hit occurs, then the Target asserts DP_START and DP_START64 in cycle 3 and claims the PCI bus by asserting DEVSELn
4. Data transfer to the backend begins on the rising edge of cycle 7 and continues for each subsequent cycle until the PCI bus ends the
5. For 64-bit transfer, the MEM_ADDRESS will increment by 2 for each cycle.
6. The PCI transaction completes when TRDYn is de-asserted in cycle 10.
7. For this case, the PIPE_FULL_CNT is set to '000' (See
8. See
Figure 9 • 64-bit Burst Write with Zero Wait States
2 6
CorePCI v5.41
and ACK64n in cycle 4.
data transfer.
"Backend Latency Control" on page 31
MEM_DATA[63:32]
WR_BE_NOW64
MEM_DATA[31:0]
MEM_ADDRESS
WR_BE_NOW
DP_START64
WR_BE_RDY
DP_START
AD[63:32]
DP_DONE
DEVSELn
AD[31:0]
FRAMEn
REQ64n
ACK64n
TRDYn
PAR64
STOPn
IRDYn
PAR
CLK
CBE
1
zero
addr
0111
for RD_CYC and BARn_CYC timing.
2
Paddr
zero
0000
0000
3
"Backend Latency Control" on page 31
data1
data0
4
v4.0
Pdata1
Pdata0
5
byte enables
add0
6
data3
data2
data1
data0
7
data5
data4
data3
add2
data2
Pd3
Pd2
8
1111
1111
data7
data6
data5
add4
data4
Pd5
Pd4
9
for more information).
data7
add6
data6
Pd7
Pd6
10
11
0000
0000
12