M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet
M471B5773DH0-YK0
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M471B5773DH0-YK0 Summary of contents
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... For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved Rev. 1.0, Sep. 2010 M471B5773DH0 M471B5273DH0 1.35V ...
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Unbuffered SODIMM Revision History Revision No. 1.0 - First Release datasheet History - 2 - Rev. 1.0 DDR3L SDRAM Draft Date Remark Editor Sep. 2010 - S.H.Kim ...
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... DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5 5. Pin Description ............................................................................................................................................................. 6 6. Input/Output Functional Description.............................................................................................................................. 8 7. Function Block Diagram: ............................................................................................................................................... 9 7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 9 7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 10 8. Absolute Maximum Ratings .......................................................................................................................................... 11 8.1 Absolute Maximum DC Ratings............................................................................................................................... 11 8.2 DRAM Component Operating Temperature Range ................................................................................................ & ...
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... Unbuffered SODIMM 1. DDR3L Unbuffered SODIMM Ordering Information 2 Part Number M471B5773DH0-YF8/H9/K0 M471B5273DH0-YF8/H9/K0 NOTE : 1. "##" - F8/H9/ 1066Mbps 7-7 1333Mbps 9-9 1600Mbps 11-11-11 - DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) 2. Key Features DDR3-800 Speed 6-6-6 tCK(min) 2.5 CAS Latency 6 tRCD(min) 15 tRP(min) ...
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... NOTE : Connect Not Usable, RFU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysis probes and normal memory modules. 3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. ...
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Unbuffered SODIMM 5. Pin Description Pin Name Description CK0, CK1 Clock Inputs, positive line CK0, CK1 Clock Inputs, negative line CKE0, CKE1 Clock Enables RAS Row Address Strobe CAS Column Address Strobe WE Write Enable S0, S1 Chip Selects A0-A9, ...
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... Input Address pins used to select the Serial Presence Detect and Temp sensor base address. TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules RESET Input RESET In Active Low This signal resets the DDR3 SDRAM ...
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... Unbuffered SODIMM 7. Function Block Diagram: 7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) Ω 240 DQS0 DQS ± 1% DQS0 DQS ZQ DM0 DM DQ[0:7] DQ[0:7] D0 Ω 240 DQS2 DQS ± 1% DQS2 DQS ZQ DM2 DM DQ[16:23] DQ[0:7] D1 Ω 240 DQS4 DQS ± 1% DQS4 ...
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... Unbuffered SODIMM 7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) Ω 240 DQS3 DQS ± 1% DQS3 DQS ZQ DM3 DM DQ[0:7] DQ[24:31] D11 Ω 240 DQS1 DQS ± 1% DQS1 DQS ZQ DM1 DM DQ[0:7] DQ[8:15] D1 Ω 240 DQS0 DQS ± 1% DQS0 DQS ZQ DM0 ...
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Unbuffered SODIMM 8. Absolute Maximum Ratings 8.1 Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to V DDQ DDQ V V Voltage on any pin relative ...
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Unbuffered SODIMM 10. AC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 1 ] Single Ended AC and DC input levels for Command and Address Symbol Parameter V (DC90) DC input ...
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Unbuffered SODIMM [ Table 2 ] Single Ended AC and DC input levels for DQ and DM Symbol Parameter V (DC90) DC input logic high IH.DQ V (DC90) DC input logic low IL.DQ V (AC160) AC input logic high IH.DQ ...
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Unbuffered SODIMM 10.2 V Tolerances REF The dc-tolerance limits and ac-noise limits for the reference voltages function of time. (V stands for V REF REF V (DC) is the linear average of V (t) over ...
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Unbuffered SODIMM 10.3 AC and DC Logic Input Levels for Differential Signals 10.3.1 Differential Signals Definition V .DIFF.AC.MIN .DIFF.AC.MAX IL Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC 10.3.2 Differential Swing Requirement for ...
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Unbuffered SODIMM [ Table 3 ] Allowed time before ringback (tDVAC) for and DQS - DQS (1.35V) Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 [ Table 4 ] Allowed ...
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Unbuffered SODIMM 10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach V SEH half-cycle. DQS ...
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Unbuffered SODIMM 10.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) ...
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Unbuffered SODIMM 10.4 Slew Rate Definition for Single Ended Input Signals See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew ...
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Unbuffered SODIMM 11.3 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V for single ended signals as shown in below. [ Table 11 ] ...
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Unbuffered SODIMM 11.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) for differential signals as shown in below. diff [ Table 13 ...
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Unbuffered SODIMM 12. IDD specification definition Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 IDD0 Command, Address, Bank Address Inputs: partially toggling ; ...
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... Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 7) IDD current measure method and detail patterns are described on DDR3 component datasheet 8) VDD and VDDQ are merged on module PCB. 9) DIMM IDD SPEC is measured with Qoff condition ...
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... Unbuffered SODIMM 13. IDD SPEC Table M471B5773DH0 : 2GB (256Mx64) Module DDR3-1066 Symbol 7-7-7 1.35V IDD0 240 IDD1 320 IDD2P0(slow exit) 80 IDD2P1(fast exit) 104 IDD2N 120 IDD2Q 120 IDD3P 120 IDD3N 200 IDD4R 440 IDD4W 480 IDD5B 880 IDD6 80 IDD7 800 IDD8 80 NOTE : 1 ...
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... DM, DQS, DQS, TDQS, TDQS) Input/output capacitance of ZQ pin NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance. 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test verified by design and characterization. ...
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Unbuffered SODIMM 15. Electrical Characteristics and AC timing [0 °C<T ≤95 ° 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); V CASE DDQ 15.1 Refresh Parameters by Device Density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval NOTE : ...
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Unbuffered SODIMM [ Table 17 ] DDR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command ...
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Unbuffered SODIMM [ Table 18 ] DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command ...
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Unbuffered SODIMM [ Table 19 ] DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command ...
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Unbuffered SODIMM 15.3.1 Speed Bin Table Notes Absolute Specification [ 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]; OPER DDQ DD NOTE : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection ...
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Unbuffered SODIMM 16. Timing Parameters by Speed Grade [ Table 20 ] Timing Parameters by Speed Bin Speed Parameter Clock Timing tCK(DLL_OF Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low ...
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Unbuffered SODIMM [ Table 20 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Symbol Data Strobe Timing DQS, DQS differential READ Preamble tRPRE DQS, DQS differential READ Postamble tRPST DQS, DQS differential output high time DQS, DQS differential output ...
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Unbuffered SODIMM [ Table 20 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Symbol Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL Exit ...
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Unbuffered SODIMM 16.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; ...
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Unbuffered SODIMM 16.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent ...
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... Unbuffered SODIMM 17. Physical Dimensions : 17.1 256Mbx8 based 256Mx64 Module (1 Rank) - M471B5773DHS 24.80 2X 1.80 0. (OPTIONAL HOLES) 1.65 1.00 ± 0.10 Detail A The used device is 256M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846D - HY** * NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified. datasheet 0.10 ...
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... Unbuffered SODIMM 17.2 256Mbx8 based 512Mx64 Module (2 Ranks) - M471B5273DH0 24.80 2X 1.80 0. (OPTIONAL HOLES) 1.65 1.00 ± 0.10 Detail A The used device is 256M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846D - HY** * NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified. datasheet 0. 67.60 63. 39.00 21.00 0.60 0.45 ± ...