SLCF2GM2TU-S STEC, SLCF2GM2TU-S Datasheet - Page 31

• Manufacturer Part Number: SLCF2GM2TU-S
• Manufacturer: STEC

Specifications of SLCF2GM2TU-S

• Lead Free Status / Rohs Status: Compliant

SLCFxxxM2TU(I)(-x)
Datasheet
t2CYCTYP
tCYC
t2CYC
tDS
tDH
tDVS
tDVH
tCS
tCH
tCVS
tCVH
tZFS
tDZFS
tFS
tLI
tMLI
tUI
tAZ
tZAH
tZAD
tENV
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
Symbol
Typical sustained average two cycle time
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)
Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling
edge to next falling edge of STROBE)
Data setup time at recipient (from data valid until STROBE edge)
Data hold time at recipient (from STROBE edge until data may become invalid)
Data valid setup time at sender (from data valid until STROBE edge)
Data valid hold time at sender (from STROBE edge until data may become invalid)
CRC word setup time at device
CRC word hold time device
CRC word valid setup time at host (from CRC valid until -DMACK negation)
CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid)
Time from STROBE output released-to-driving until the first transition of critical timing.
Time from data output released-to-driving until the first transition of critical timing.
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to release (from asserted or negated)
Minimum delay time required for output
Drivers to assert or negate (from released)
Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and from
DMACK to STOP during data out burst initiation)
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of -
DMARDY)
Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)
Maximum time before releasing IORDY
Minimum time before driving IORDY
Setup and hold times for -DMACK (before assertion or negation)
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender
terminates a burst)
Table 23: UDMA Timing Parameter Descriptions
61000-07000-104, April 2011
Parameter
CompactFlash Card
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