PIC32MX440F128L-80V/BG Microchip Technology, PIC32MX440F128L-80V/BG Datasheet - Page 129

• Manufacturer Part Number: PIC32MX440F128L-80V/BG
• Description: 128 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128L-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

25.0
This
PIC32MX3XX/4XX. The PIC32MX devices offer a total
of nine methods and modes that are organized into two
categories that allow the user to balance power con-
sumption with device performance. In all of the meth-
ods and modes described in this section, power-saving
is controlled by software.
25.1
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK, and by individually disabling modules.
These methods are grouped into the following modes:
• FRC Run mode: the CPU is clocked from the FRC
• LPRC Run mode: the CPU is clocked from the
• S
• Peripheral Bus Scaling mode: peripherals are
25.2
The device supports two power-saving modes, Sleep
and Idle, both of which halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• P
• FRC Idle Mode: the system clock is derived from
• S
© 2011 Microchip Technology Inc.
clock source with or without postscalers.
LPRC clock source.
S
clocked at programmable fraction of the CPU
clock (SYSCLK).
the P
operate.
Peripherals continue to operate, but can
optionally be individually disabled.
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
the S
can optionally be individually disabled.
Note 1: This data sheet summarizes the features
OSC
OSC
OSC
OSC
section
OSC
OSC
Run mode: the CPU is clocked from the
clock source.
Idle Mode: the system clock is derived from
Idle Mode: the system clock is derived from
2: Some registers and associated bits
POWER-SAVING FEATURES
Power-Saving with CPU Running
CPU Halted Methods
. The system clock source continues to
. Peripherals continue to operate, but
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 10. “Power-Saving
Features” (DS61130) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
describes
power-saving
for
the
in
• LPRC Idle Mode: the system clock is derived from
• Sleep Mode: the CPU, the system clock source,
25.3
The purpose of all power-saving is to reduce power
consumption by reducing the device clock frequency.
To achieve this, low-frequency clock sources can be
selected. In addition, the peripherals and CPU can be
halted
consumption.
25.3.1
Sleep mode has the lowest power consumption of the
device Power-Saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual periph-
eral module sections for descriptions of behavior in
Sleep mode.
Sleep mode includes the following characteristics:
• The CPU is halted.
• The system clock source is typically shut down.
• There can be a wake-up delay based on the
• The Fail-Safe Clock Monitor (FSCM) does not
• The BOR circuit, if enabled, remains operative
• The WDT, if enabled, is not automatically cleared
• Some peripherals can continue to operate in
• I/O pins continue to sink or source current in the
• The USB module can override the disabling of the
• Some modules can be individually disabled by
the LPRC.
Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
power mode for the device with a clock running.
and any peripherals that operate from the system
clock source, are halted.
Some peripherals can operate in Sleep using spe-
cific clock sources. This is the lowest power mode
for the device.
See
information.
oscillator selection.
operate during Sleep mode.
during Sleep mode.
prior to entering Sleep mode.
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, WDT,
ADC, UART and peripherals that use an external
clock input or the internal LPRC oscillator, e.g.,
RTCC and Timer 1.
same manner as they do when the device is not in
Sleep.
P
The-Go (OTG)”
software prior to entering Sleep in order to further
reduce consumption.
OSC
Section 25.3.2 “Idle Mode”
PIC32MX3XX/4XX
or FRC. Refer to
or
Power-Saving Operation
SLEEP MODE
disabled
for specific details.
to
Section 11.0 “USB On-
further
DS61143H-page 129
for specific
reduce
power