PIC32MX440F128L-80V/BG Microchip Technology, PIC32MX440F128L-80V/BG Datasheet - Page 50

• Manufacturer Part Number: PIC32MX440F128L-80V/BG
• Description: 128 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128L-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

TABLE 4-1:
Legend:
Note
2000
2010
2020
2030
2040
2050
2060
2070
1:
DKPBA
DUDBA
DUPBA
PUPBA
BOOTSZ
DRMSZ
PFMSZ
CON
BMX
BMX
BMX
BMX
BMX
BMX
BMX
BMX
(1)
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
BUS MATRIX REGISTERS MAP
31/15
—
—
—
—
—
—
30/14
—
—
—
—
—
—
29/13
—
—
—
—
—
—
28/12
—
—
—
—
—
—
27/11
—
—
—
—
—
—
BMXCHEDMA
26/10
—
—
—
—
—
25/9
—
—
—
—
—
—
24/8
—
—
—
—
—
—
BMXBOOTSZ<31:0>
BMXDUDBA<15:0>
BMXDUPBA<15:0>
BMXDRMSZ<31:0>
BMXDKPBA<15:0>
BMXPUPBA<15:0>
BMXPFMSZ<31:0>
23/7
—
—
—
—
—
—
Bits
BMXWSDRM
22/6
—
—
—
—
—
21/5
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
20/4
—
—
—
—
—
19/3
—
—
—
—
BMXPUPBA<19:16>
18/2
—
—
—
BMXARB<2:0>
for more information.
17/1
—
—
—
16/0
—
—
—
0042
0000
0000
0000
0000
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
3000