CY7B933-SC Cypress Semiconductor Corp, CY7B933-SC Datasheet
CY7B933-SC
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CY7B933-SC Summary of contents
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... HOTLink devices are ideal for a variety of applications where a parallel interface can be replaced with a high-speed point-to-point serial link. Applications include interconnecting workstations, servers, mass storage, and video transmission equipment. CY7B933 Receiver Logic Block Diagram ) a RF SVS(D ) A/B ...
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... PLCC/LCC Top View 2726 28 BISTEN 5 GND 6 MODE 7 7B923 CCQ SVS 1213 14 15 1718 Document #: 38-02017 Rev. *C SERIAL LINK Figure 1. HOTLink System Connections CY7B933 Receiver Pin Configurations OUTB+ 28 OUTA OUTA FOTO 25 ENN 24 ENA CCQ CKW 21 GND 20 SC/D FOTO 25 24 ENN 23 ENA 22 V CCQ ...
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... SVS has the same timing reduce power, if the output is not required. OUTA± and OUTB± CC goes directly to the shifter. When left floating (internal resistors hold the input a-j CY7B923 CY7B933 , respectively. ) acts as D input. SC/D has the a a and SC/D determines 0 7 ...
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... RP will remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop. V Power for output drivers. CCN V Power for internal circuitry. CCQ GND Ground. CY7B933 HOTLink Receiver Name I/O Description Q TTL Out Q0-7 Parallel Data Output synchronously with CKR ...
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... CY7B933 HOTLink Receiver (continued) Name I/O Description REFCLK TTL In Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL. REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream. REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within CKW 0 ...
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... Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic to properly select the data encoding. Test logic is discussed in more detail in the CY7B923 HOTLink Transmitter Operating Mode Description. CY7B933 HOTLink Receiver Block Diagram Description Serial Data Inputs Two pairs of differential line receivers are the inputs for the serial data stream. INA± ...
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... K28.5’s. The latency through the receiver is approximately 24t operating range. A more complete description of the receiver is in the section CY7B933 HOTLink Receiver Operating Mode Description. The HOTLink Receiver has a built-in byte framer that synchro- nizes the Receiver pipeline with incoming SYNC (K28.5) characters ...
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... SERIAL DATA IN INX CKR Q0 7, DATA SC/D, RVS RDY RDY IS LOW FOR DATA Figure 2. CY7B933 Receiver Data Pipeline in Encoded Mode RF LATCHED ON FALLING EDGE OF CKR CKR SC/D, DATA DATA RVS RDY Figure 3. CY7B933 Framing Operation in Encoded Mode When the RF pin is asserted HIGH, RDY leaves it normal mode of operation and is asserted HIGH while the framer searches the data stream for a K28 ...
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... HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0) to maintain proper link synchronization (in Bypass = 111 00000 and SC/D 7-0 CLOCKED FIFO 7C44X/5X ENR CKR ENN CKW D ,SC 7B923 HOTLINK TRANSMIT TER HOTLINK RECEIVER 7B933 CKR RDY Q ,SC CKW ENW 7C44X/5X CLOCKED FIFO CY7B923 CY7B933 B923–21 Page ...
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... Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver, and the link connecting them. This mode is available with minimal impact on user system logic, and can be used as part of the normal system diagnostics. Typical connections and timing are shown in Figure 6. CY7B923 CY7B933 Page ...
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... E IB– (Qa) (Qb) (Qc) (Qd (Qe) IA (Qi) IA– (Qf) (Qg) (Qh) (Qj) GND Figure 5. HOTLink Connection Diagram CY7B923 CY7B933 .01UF VCC 130 Fiber Optic Fiber Tx TX TX+ TX– 130 GND Coax or Twisted Pair A B 270 270 .01UF 649 1500 RL/2 Coax or Twisted Pair RL/2 Optional Signal Det ...
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... SVS input, or allowing the trans- mitter BIST loop to run while the Receiver runs in normal mode. The BIST loop includes deliberate violation symbols and will adequately test the RVS function. CY7B923 CY7B933 CY7B923 OUTA OUTB OUTC CY7B933 SO DON’T CARE INA INB LOW A/B Page ...
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... HIGH while in Test mode. This forces the two outputs “PECL LOW,” which can be ignored while the test system creates a differential input signal at some higher voltage. CY7B933 HOTLink Receiver Operating Mode Description In normal user operation, the Receiver can operate in either of two modes. The Encoded mode allows a user system to send Document #: 38-02017 Rev ...
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... In Bypass mode with RF HIGH, RDY will pulse once for each K28.5 received. For more information on the RDY pin, consult the “HOTLink CY7B933 RDY Pin Description” appli- cation note. Code rule violations and reception errors will be indicated as follows: Document #: 38-02017 Rev ...
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... Receiver Test Mode Description The CY7B933 Receiver offers two types of test mode operation, BIST mode and Test mode normal system application, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver and the link connecting them. This mode is available with minimal impact on user system logic, and can be used as part of the normal system diagnostics ...
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... It is also pos- itive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones also CY7B923 CY7B933 Page ...
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... Transmission Character in which the error occurred. Table 2 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CY7B923 CY7B933 Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 . ...
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... D0.2 010 00000 100111 100001 1011 D1.2 010 00001 011101 010100 1011 D2.2 010 00010 101101 011000 1001 D3.2 010 00011 110001 100010 1001 CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1001 010010 1001 110001 1001 001010 1001 ...
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... D6.4 100 00110 011001 001010 1100 D7.4 100 00111 111000 101001 0011 D8.4 100 01000 111001 011001 0011 D9.4 100 01001 100101 CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1100 000111 0011 000110 1100 100101 1100 ...
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... D12.6 110 01100 001101 010101 1010 D13.6 110 01101 101100 110100 1010 D14.6 110 01110 011100 001101 1010 D15.6 110 01111 010111 CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1010 101100 1010 011100 1010 101000 1010 ...
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... CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1110 110010 0111 001011 1110 101010 1110 011010 0001 000101 0001 ...
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... Code Rule Violation and SVS Tx Pattern 111 00000 100111 111 00001 001111 111 00010 110000 Running Disparity Violation Pattern 111 00100 110111 CY7B923 CY7B933 Current RD+ fghj abcdei fghj 0100 110000 1011 1001 110000 0110 0101 110000 1010 0011 110000 1100 ...
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... TTL OUTs, CY7B923: RP; CY7B933 Output HIGH Voltage OHT V Output LOW Voltage OLT I Output Short Circuit Current OST TTL INs, CY7B923 SC/D, SVS, ENA, ENN, CKW, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN Input HIGH Voltage IHT V Input LOW Voltage ILT I Input HIGH Current IHT ...
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... CY7B923/CY7B933 Electrical Characteristics Parameter Description Miscellaneous [11] I Transmitter Power Supply CCT Current [12] I Receiver Power Supply CCR Current [13] Capacitance Parameter Description C Input Capacitance IN AC Test Loads and Waveforms OUTPUT R 1= 910 510 L C < (Includes fixture and probe capacitance) (a) TTL AC Test Load 3 ...
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... –3 5t – –2.5 t –2 –3 5t – –3 4t – – – –2.5 t –2 –3 2t – +0.1 –0.1 +0.1 –0 pF. L 1.35V). The TTL switching threshold is 1.5V. CC CY7B923 CY7B933 Max Unit 62 1 175 Max. Unit + +0.1 % Page ...
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... Min. 6.5 6.5 0. CPWL t SENP t t HENP SD 16,17 NOTES VALID DATA PDF t PDR t PPWH t CKW t CPWH t CPWL CY7B923 CY7B933 [7] 7B933 7B933-400 Max Min. Max. Min. Max. 6.5 6.5 6.5 6 100 100 0.9t 0. CKW t CPWH DISABLED ENABLED VALID DATA Page Unit ...
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... Switching W0aveforms for the CY7B933 HOTLink Receiver CKR RDY SC/D,RVS, REFCLK NOTE SO Static Alignment INA , INB SAMPLE WINDOW Document #: 38-02017 Rev CPRH t CPRL t PRH t PRF CPXL t CPXH t DS 1.5V Error-free Window CKR ROH t CKX t EFW INA INB t B BIT CENTER BIT CENTER ...
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... CY7B923-400JC CY7B923-400JI 155 CY7B923-155JC CY7B923-155JI Standard CY7B933-JC CY7B933-JI CY7B933-SC 400 CY7B933-400JC CY7B933-400JI 155 CY7B933-155JC CY7B933-155JI Notes: 29. C1.7 = Transmit Negative K28.5 (–K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C1.7 if K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7. 30. C2.7 = Transmit Positive K28.5 (+K28.5– ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-lead Plastic Leaded Chip Carrier J64 28-lead (300-mil) Molded SOIC S21 CY7B923 CY7B933 51-85001-A 51-85026-A Page ...
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... Document History Page Document Title: CY7B923/CY7B933 HOTLink Transmitter/Receiver Document Number: 38-02017 Issue REV ECN NO. Date ** 105855 03/28/01 *A 112164 03/25/02 *B 114562 03/27/02 *C 125525 04/01/03 Document #: 38-02017 Rev. *C Orig. of Change SZV Changed from Spec number: 38-00189 to 38-02017 REV Changed OUTA± pin description to improve consistency with diagram. ...