DP8392CN National Semiconductor, DP8392CN Datasheet

IC TRANSCEIVER COAX INT 16-DIP

DP8392CN

Manufacturer Part Number
DP8392CN
Description
IC TRANSCEIVER COAX INT 16-DIP
Manufacturer
National Semiconductor
Type
Transceiverr
Datasheet

Specifications of DP8392CN

Protocol
IEEE 802
Voltage - Supply
9V
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Dc
00+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Other names
*DP8392CN

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C 1995 National Semiconductor Corporation
DP8392A NS32492A Coaxial Transceiver Interface
General Description
The DP8392A Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver receiver for Ethernet Thin Ethernet
(Cheapernet) type local area networks The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE) In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable In Cheapernet applica-
tions the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only The
CTI consists of a Receiver Transmitter Collision Detector
and a Jabber Timer The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting During transmission a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision
The CTI is part of a three chip set that implements the com-
plete IEEE 802 3 compatible network node electronics as
shown below The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC)
The SNI provides the Manchester encoding and decoding
functions whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks Isolation between
the CTI and the SNI is an IEEE 802 3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP However the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
TL F 7405
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Table of Contents
1 0 System Diagram
2 0 Block Diagram
3 0 Functional Description
3 1
3 2
3 3
3 4
4 0 Connection Diagram
5 0 Pin Descriptions
6 0 Absolute Maximum Ratings
7 0 Electrical Characteristics
8 0 Switching Characteristics
9 0 Timing and Load Diagram
10 0 Physical Dimensions
Compatible with Ethernet II IEEE 802 3 10Base5 and
10Base2 (Cheapernet)
Integrates all transceiver electronics except signal
power isolation
Innovative design minimizes external component count
Jabber timer function integrated on chip
Externally selectable CD Heartbeat allows operation
with IEEE 802 3 compatible repeaters
Precision circuitry implements receive mode collision
detection
Squelch circuitry at all inputs rejects noise
Designed
IEEE 802 3
Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Receiver and Squelch
Transmitter and Squelch
Collision and Heartbeat
Jabber Timer
for
rigorous
reliability
RRD-B30M105 Printed in U S A
requirements
TL F 7405 – 1
May 1988
of

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DP8392CN Summary of contents

Page 1

... DIP However the power isolation for the CTI is done by DC-to-DC conversion through a power transformer 1 0 System Diagram IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set C 1995 National Semiconductor Corporation TL F 7405 Features Compatible with Ethernet II IEEE 802 3 10Base5 and Y ...

Page 2

Block Diagram 3 0 Functional Description The CTI consists of four main logical blocks a) the Receiver - receives data from the coax and sends it to the DTE b) the Transmitter - accepts data from the DTE ...

Page 3

Functional Description 3 3 COLLISION FUNCTIONS The collision circuitry consists of two buffers two 4-pole Bessel low pass filters (section comparator a heart- beat generator a 10 MHz oscillator and a differential line driver Two ...

Page 4

Connection Diagram Note pulse transformer L 100 H e Pulse Engineering (San Diego) Part No 64103 Valor Electronics (San Diego) Part No 1101 or equivalent Top View Order Number DP8392AN See NS ...

Page 5

... pins are to be connected to a copper plane which EE should be included in the printed circuit board layout Refer to National Semiconductor application note AN-442 (Ether- net Cheapernet Physical Layer Made Easy) for complete board layout instructions 5 drop cable is not used ...

Page 6

... A Recommended Operating (Note 1) Conditions 12V Watts Supply Voltage (V EE See Section 5 Ambient Temperature If Military Aerospace specified devices are required 0 to 12V b please contact the National Semiconductor Sales 65 to 150 C b Office Distributors for availability and specifications 260 (Notes Min pin non transmitting ...

Page 7

Timing and Load Diagrams FIGURE 5 Receiver Timing FIGURE 6 Transmitter Timing FIGURE 7 Collision Timing FIGURE 8 Heartbeat Timing 7405 – 7405 – 7405 – ...

Page 8

Timing and Load Diagrams The 50 H inductance is for testing purposes Pulse transformers with higher inductances are recommended (see Figure 4 ) (Continued) FIGURE 9 Jabber Timing Input jitter Output jitter 7 ...

Page 9

9 ...

Page 10

... Floor Straight Block a Ocean Centre 5 Canton Rd 49) 0-180-530 85 85 Tsimshatsui Kowloon a Tel ( 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 a Tel ( 49) 0-180-534 16 80 Fax (852) 2736-9960 a Lit 103054 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...

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