ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 17

• Manufacturer Part Number: ATTINY12-8SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
• Manufacturer: Atmel

Specifications of ATTINY12-8SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Lead Free Status / Rohs Status: Details

Flash Program Memory
EEPROM Data Memory
Prevent EEPROM
Corruption
ATtiny12 EEPROM
Read/Write Access
1006F–AVR–06/07
The ATtiny11/12 contains 1K bytes on-chip Flash memory for program storage. Since
all instructions are single 16-bit words, the Flash is organized as 512 x 16 words. The
Flash memory has an endurance of at least 1000 write/erase cycles.
The ATtiny11/12 Program Counter is 9 bits wide, thus addressing the 512 words Flash
program memory.
See “Memory Programming” on page 48 for a detailed description on Flash memory
programming.
The ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endur-
ance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described on page 18, specifying the EEPROM Address Register, the EEPROM
Data Register, and the EEPROM Control Register.
For SPI data downloading, see “Memory Programming” on page 48 for a detailed
description.
During periods of low V
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board-level systems using the EEPROM, and the same design solutions
should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the
supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommen-
dations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply
2. Keep the AVR core in Power-down Sleep Mode during periods of low V
Store constants in Flash memory if the ability to change memory contents from software
is not required. Flash memory can not be updated by the CPU, and will not be subject to
corruption.
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 3.1 - 6.8 ms, depending on the frequency of the
calibrated RC oscillator. See Table 6 for details. A self-timing function lets the user soft-
ware detect when the next byte can be written. A special EEPROM Ready interrupt can
be set to trigger when the EEPROM is ready to accept new data. The minimum voltage
for writing to the EEPROM is 2.2V.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed. When the EEPROM is read, the CPU is halted for four clock
cycles before the next instruction is executed.
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if
the operating speed matches the detection level. If not, an external low V
Reset Protection circuit can be applied.
will prevent the CPU from attempting to decode and execute instructions, effec-
tively protecting the EEPROM registers from unintentional writes.
CC
, the EEPROM data can be corrupted because the supply volt-
ATtiny11/12
CC
CC
. This
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