ADV7191KST Analog Devices Inc, ADV7191KST Datasheet - Page 37

• Manufacturer Part Number: ADV7191KST
• Description: IC VIDEO ENCODER W/6DAC 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7191KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0
(PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)
(Subaddress (SR4–SR0) = 15–18H)
These 8-bit-wide registers are used to enable the NTSC pedestal/
PAL Teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 66 and 67 show
the four control registers. A Logic 1 in any of the bits of these
registers has the effect of turning the Pedestal OFF on the equiva-
lent line when used in NTSC. A Logic 1 in any of the bits of
these registers has the effect of turning Teletext ON on the
equivalent line when used in PAL.
TELETEXT REQUEST CONTROL REGISTER (TC07–TC00)
(Address (SR4–SR0) = 1CH)
Teletext Control Register is an 8-bit-wide register. See Figure 68.
TTXREQ Falling Edge Control (TC00–TC03)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero clock cycles to a maximum
of 15 clock cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext bits
below the default of 360. If Bits TC00–TC03 are 00Hex when
REV. B
FIELD 1/3
FIELD 2/4
FIELD 1/3
FIELD 2/4
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10
LINE 17 LINE 16
LINE 25 LINE 24 LINE 23
LINE 17 LINE 16
LINE 25 LINE 24 LINE 23
PCE15
LINE 14 LINE 13
LINE 22 LINE 21 LINE 20
LINE 14 LINE 13
LINE 22 LINE 21 LINE 20
TXO15
TXE15
PCO7
PCE7
TXO7
TXE7
Figure 66. Pedestal Control Registers
Figure 67. Teletext Control Registers
PCE14
TXO14
TXE14
PCO6
PCE6
TXO6
TXE6
LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE13
LINE 12 LINE 11 LINE 10
TXO13
LINE 12 LINE 11 LINE 10
TXE13
PCO5
PCE5
TXO5
TXE5
C/W07
WSS CONTROL
0
1
LINE 22 LINE 21 LINE 20
LINE 22 LINE 21 LINE 20
PCE12
LINE 19 LINE 18 LINE 17
LINE 19 LINE 18 LINE 17
TXO12
TXE12
PCO4
PCE4
TXO4
TXE4
C/W07
DISABLE
ENABLE
C/W06
PCE11
CGMS EVEN FIELD
TXO11
TXE11
PCO3
PCE3
TXO3
TXE3
0
1
CONTROL
C/W06
DISABLE
ENABLE
PCE10
TXO10
TXE10
PCO2
PCE2
LINE 9
LINE 9
TXO2
TXE2
C/W05
CGMS ODD FIELD
Figure 69. CGMS_WSS Register 0
0
1
LINE 19 LINE 18
CONTROL
LINE 19 LINE 18
LINE 16 LINE 15
LINE 16 LINE 15
PCO1
PCO9
LINE 8
LINE 8
PCE1
PCE9
TXO9
TXO1
TXE1
TXE9
C/W05
DISABLE
ENABLE
C/W04
CGMS CRC CHECK
LINE 7
LINE 7
PCO0
PCO8
PCE0
PCE8
TXO8
TXO0
TXE0
TXE8
0
1
CONTROL
C/W04
DISABLE
ENABLE
–37–
Bits TC07–TC04 are changed then the falling edge of TTREQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant).
PCLK = clock cycle at 27 MHz.
TTXREQ Rising Edge Control (TC04–TC07)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero clock cycles to a maximum of 15
clock cycles.
PCLK = clock cycle at 27 MHz.
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address (SR4–SR0) = 19H)
CGMS_WSS register 0 is an 8-bit-wide register. Figure 69 shows
the operations under control of this register.
C/W0 BIT DESCRIPTION
CGMS Data (C/W00–C/W03)
These four data bits are the final four bits of CGMS data output
stream. Note it is CGMS data ONLY in these bit positions, i.e.,
WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (1), the last six bits of the CGMS data,
i.e., the CRC check sequence, is internally calculated by the
ADV7190/ADV7191. If this bit is disabled (0), the CRC values
in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (1), CGMS is enabled for odd fields. Note
this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (1), CGMS is enabled for even fields. Note
this is only valid in NTSC mode.
WSS Control (C/W07)
When this bit is set (1), wide screen signalling is enabled. Note
this is only valid in PAL mode.
C/W03
TC07
TC07 TC06 TC05 TC04
0
0
''
1
1
RISING EDGE CONTROL
0
0
''
1
1
TC06
C/W02
Figure 68. Teletext Control Register
TTXREQ
C/W03 – C/W00
0
0
''
1
1
CGMS DATA
TC05
0
1
''
0
1
C/W01
0 PCLK
1 PCLK
'' PCLK
14 PCLK
15 PCLK
TC04
ADV7190/ADV7191
C/W00
TC03
TC03 TC02 TC01 TC00
0
0
''
1
1
FALLING EDGE CONTROL
0
0
''
1
1
TC02
TTXREQ
0
0
''
1
1
0
TC01
''
1
0
1
0 PCLK
1 PCLK
'' PCLK
14 PCLK
15 PCLK
TC00