ADV7191KST Analog Devices Inc, ADV7191KST Datasheet - Page 49

• Manufacturer Part Number: ADV7191KST
• Description: IC VIDEO ENCODER W/6DAC 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7191KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

Time, t
interpolate input data on TTX and insert it onto the CVBS
or Y outputs, such that it appears t
leading edge of the horizontal signal. Time, TTX
pipeline delay time by the source that is gated by the TTXREQ
signal in order to deliver TTX data.
With the programmability that is offered with TTXREQ signal
on the Rising/Falling edges, the TTX data is always inserted at
the correct position of 10.2 ms after the leading edge of Horizontal
Sync pulse, which enables a source interface with variable pipe-
line delays.
The width of the TTXREQ signal must always be maintained
so it allows the insertion of 360 (in order to comply with the
Teletext Standard PAL-WST) teletext bits at a text data rate of
6.9375 Mbits/s. This is achieved by setting TC03–TC00 to 0.
The insertion window is not open if the Teletext Enable bit
(MR33) is set to 0.
REV. B
PD
, is the time needed by the ADV7190/ADV7191 to
TTX
TTXREQ
CVBS/Y
HSYNC
DATA
t
t
TTX
SYNTTXOUT
PD
TELETEXT VBI LINE
= PIPELINE DELAY THROUGH ADV7190/ADV7191
DEL
t
PD
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
= 10.2 s
TTX
SYNTTXOUT
ST
10.2 s
t
SYNTTXOUT
Figure 93. Teletext Functionality Diagram
TTX
= 10.2 ms after the
DEL
DEL
Figure 92. Teletext VBI Line
, is the
TELETEXT INSERTION
t
PD
APPENDIX 5
RUN-IN CLOCK
45 BYTES (360 BITS) – PAL
PROGRAMMABLE PULSE EDGES
–49–
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is given as follows:
Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit
has a width of almost four clock cycles. The ADV7190/ADV7191
uses an internal sequencer and variable phase interpolation filter
to minimize the phase jitter and thus generate a bandlimited
signal which can be output on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that
TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are Bits 47, 56, 65, and 74. This scheme
holds for all following cycles of 37 TTX bits, until all 360 TTX
bits are completed. All teletext lines are implemented in the
same way. Individual control of teletext lines are controlled
by Teletext Setup Registers.
ADDRESS & DATA
(6.9375 ¥ 10
(27 MHz/4) = 6.75 MHz
6
/6.75 ¥ 10
ADV7190/ADV7191
6
= 1.027777