ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet - Page 12

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ADV7183AKST

Manufacturer Part Number
ADV7183AKST
Description
IC VIDEO DECODER NTSC 80-LQFP
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet

Specifications of ADV7183AKST

Applications
Projectors, Recorders, Security
Voltage - Supply, Analog
3.15 V ~ 3.45 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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ADV7183A
Pin No.
27
26
29
28
36
79
37
12
51
52
48, 49
54, 55
Mnemonic
LLC1
LLC2
XTAL
XTAL1
PWRDN
OE
ELPF
SFL
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
Type
O
O
I
O
I
I
I
O
O
O
I
I
Function
This is a line-locked output clock for the pixel data output by the ADV7183A. Nominally
27 MHz, but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the
ADV7183A. Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183A. In crystal mode, the
crystal must be a fundamental crystal.
A logic low on this pin places the ADV7183A in a power-down mode. Refer to the I2C
Control Register Map for more options on power-down modes for the ADV7183A.
When set to a logic low, OE enables the pixel output bus, P15–P0 of the ADV7183A. A logic
high on the OE pin places Pins P15–P0, HS, VS, SFL into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 43.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital
video encoder.
Internal Voltage Reference Output. Refer to Figure 43 for a recommended capacitor
network for this pin.
Common-Mode Level for the Internal ADCs. Refer to Figure 43 for a recommended
capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 43 for a recommended capacitor network for
this pin.
ADC’s Capacitor Network. Refer to Figure 43 for a recommended capacitor network for
this pin.
Rev. B | Page 12 of 104

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