ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet
ADV7183AKST
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ADV7183AKST Summary of contents
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FEATURES Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, 10-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™) 5-line adaptive comb filters Proprietary architecture for locking ...
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ADV7183A TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Functional Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ ...
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REVISION HISTORY 3/05—Rev Rev. B Added NTSC J ...................................................................................1 Changes to the Analog Specifications Section.........................8 Changes to Figure 5 ........................................................................11 Changes to Table 9 ........................................................................14 Addition to Clamp Section....................................................... Changes to Figures 12.....................................................................30 Changes to Figures 13, 14, ...
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ADV7183A INTRODUCTION The ADV7183A is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced ...
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FUNCTIONAL BLOCK DIAGRAM FORMATTER OUTPUT Figure 1. Rev Page 5 of 104 ADV7183A 04821-001 ...
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ADV7183A SPECIFICATIONS Temperature range –40°C to +85°C. The min/max specifications are guaranteed over this range. MIN MAX ELECTRICAL CHARACTERISTICS VDD VDD ...
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VIDEO SPECIFICATIONS Guaranteed by characterization 3. 3. VDD temperature range, unless otherwise noted. Table 2. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End Crosstalk LOCK TIME ...
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ADV7183A TIMING SPECIFICATIONS Guaranteed by characterization 3. 3. VDD temperature range, unless otherwise noted. Table 3. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability PORT SCLK Frequency SCLK Min Pulse ...
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TIMING DIAGRAMS t 3 SDA SCLK OUTPUT LLC1 OUTPUT LLC2 OUTPUTS P0–P15, VS, HS, FIELD, SFL P0–P15, HS, VS, FIELD, SFL Figure Timing ...
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ADV7183A ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to GND 4 V VDD A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO D to ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS HS DGND DVDDIO P11 P10 P9 P8 DGND DVDD NC SFL NC DGND DVDDIO CONNECT Table 7. Pin Function Descriptions Pin No. Mnemonic 3, 9, 14, ...
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ADV7183A Pin No. Mnemonic 27 LLC1 26 LLC2 29 XTAL 28 XTAL1 36 PWRDN ELPF 12 SFL 51 REFOUT 52 CML 48, 49 CAPY1, CAPY2 54, 55 CAPC1, CAPC2 Type Function O This is a line-locked output ...
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ANALOG FRONT END ANALOG INPUT MUXING The ADV7183A has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. Figure 6 outlines the overall structure of the input muxing provided ...
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ADV7183A SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION Table 8. Input Channel Switching Using INSEL[3:0] INSEL[3:0] Analog Input Pins 0000 CVBS1 = AIN1 (default) 0001 CVBS2 = AIN2 0010 CVBS3 = AIN3 0011 CVBS4 = AIN4 0100 CVBS5 = AIN5 0101 ...
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Manual Input Muxing By accessing a set of manual override muxing registers, the analog input muxes of the ADV7183A can be controlled directly. This is referred to as manual input muxing. Notes • Manual input muxing overrides other input muxing ...
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ADV7183A GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. POWER-SAVE MODES Power-Down PDBP, Address 0x0F [2] There are two ways to shut down the digital core of the ADV7183A: a pin ( PWRDN ) ...
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GLOBAL PIN CONTROL Three-State Output Drivers TOD, Address 0x03 [6] This bit allows the user to three-state the output drivers of the ADV7183A. Upon setting the TOD bit, the P15–P0, HS, VS, FIELD, and SFL pins are three-stated. The timing ...
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ADV7183A Drive Strength Selection (Clock) DR_STR_C[1:0] Address 0x0E [3:2] The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the following sections: • Drive Strength Selection (Sync) ...
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GLOBAL STATUS REGISTERS There are four registers that provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7183A. The other three registers contain status bits from the ADV7183A. IDENTIFICATION ...
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ADV7183A STATUS 2 STATUS_2[7:0], Address 0x12 [7:0] Table 28. STATUS 2 Function STATUS 2 [7:0] Bit Name 0 MVCS DET 1 MVCS T3 2 MV_PS DET 3 MV_AGC DET 4 LL_NSTD 5 FSC_NSTD 6 Reserved 7 Reserved STATUS 3 STATUS_3[7:0], ...
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STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION LUMA DIGITIZED CVBS DIGITAL DIGITIZED Y (YC) FINE CLAMP CHROMA DIGITIZED CVBS DIGITAL CHROMA DIGITIZED C (YC) FINE DEMOD CLAMP RECOVERY A block diagram of the ADV7183A’s standard definition processor (SDP) ...
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ADV7183A SYNC PROCESSING The ADV7183A extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources, for example videocassette recorders with head switches. ...
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AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video, Address 0x07 [7] Table 31. AD_SEC525_EN Function AD_SEC525_EN Description 0 (default) Disable the autodetection of a 525-line system with a SECAM style, FM-modulated color component. 1 Enable the detection. AD_SECAM_EN Enable Autodetection ...
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ADV7183A Lock Related Controls Lock information is presented to the user through Bits [1:0] of the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0] section. Figure 9 outlines the signal flow and the controls available to influence the way ...
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COLOR CONTROLS The following registers provide user control over the picture appearance, including control of the active data in the event of video being lost. They are independent of any other controls. For instance, brightness control is independent from picture ...
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ADV7183A BRI[7:0] Brightness Adjust, Address 0x0A [7:0] This register controls the brightness of the video signal through the ADV7183A. Table 50. BRI Function BRI[7:0] Description (Adjust Brightness of the Picture) 0x00 (default) Offset of the luma channel = +0IRE. 0x7F ...
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CLAMP OPERATION FINE CURRENT SOURCES ANALOG VIDEO INPUT The input video is ac-coupled into the ADV7183A through a 0.1 µF capacitor recommended that the range of the input video signal is 0 1.6 V (typically 1 ...
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ADV7183A DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5] The Clamp Timing register determines the time constant of the digital fine clamp circuitry important to realize that the digital fine clamp reacts very fast since it is supposed to ...
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The luma shaping filter has three control registers: • YSFM[4:0] allows the user to manually select a shaping filter mode (applied to all video signals enable an automatic selection (dependent on video quality and video standard). • WYSFMOVR ...
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ADV7183A Table 60. YSFM Function YSFM[4:0] Description 0'0000 Automatic selection including a wide notch response (PAL/NTSC/SECAM) 0'0001 Automatic selection including a narrow notch response (PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 ...
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COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant) COMBINED Y ANTIALIAS, PAL NOTCH FILTERS, ...
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ADV7183A COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER 0 –10 –20 –30 –40 –50 – FREQUENCY (MHz) Figure 16. Chroma Shaping Filter Responses GAIN OPERATION The gain control within the ADV7183A is done on ...
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Luma Gain LAGC[2:0] Luma Automatic Gain Control, Address 0x2C [7:0] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. There are ADI internal parameters to customize the peak white ...
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ADV7183A BETACAM Enable Betacam Levels, Address 0x01 [5] If YPrPb data is routed through the ADV7183A, the automatic gain control modes can target different video input levels, as outlined in Table 71. The BETACAM bit is valid only if the ...
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CG[11:0] Chroma Gain, Address 0x2D [3:0]; Address 0x2E [7:0] CMG[11:0] Chroma Manual Gain, Address 0x2D [3:0]; Address 0x2E [7:0] Chroma gain [11: dual-function register: • If written to, a desired manual chroma gain can be programmed. This gain ...
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ADV7183A CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the ...
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DIGITAL NOISE REDUCTION (DNR) Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise, and that their removal therefore improves picture quality. DNR_EN Digital Noise Reduction Enable, Address 0x4D [5] The DNR_EN ...
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ADV7183A CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3] Table 83. CCMN Function CCMN[2:0] Description 0xx (default) Adaptive comb mode. 100 Disable chroma comb. 101 Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of ...
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PAL Comb Filter Settings Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, PAL-60 and NTSC443 CVBS inputs. PSFSEL[1:0] Split Filter Selection PAL, Address 0x19 [1:0] The PSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A ...
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ADV7183A AV CODE INSERTION AND CONTROLS 2 This section describes the I C based controls that affect • Insertion of AV codes into the data stream • Data blanking during the vertical blank interval (VBI) • The range of data ...
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BL_C_VBI Blank Chroma During VBI, Address 0x04 [2] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines get blanked. This is done so any data that may come during VBI is not decoded as color and output ...
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ADV7183A SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: • Beginning of HS signal via HSB[10:0]. • End of HS signal via HSE[10:0]. • Polarity of HS ...
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VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as the generation of embedded AV codes: • ADV encoder-compatible signals via NEWAVMODE • PVS, PF • ...
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ADV7183A VSEHE VS End Horizontal Position Even, Address 0x33 [6] The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow-on chips require the ...
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OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT 262 263 264 265 266 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT Figure 22. NTSC Typical VSync/Field Positions Using Register Writes in Table 109 Table 109. Recommended ...
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ADV7183A 1 NVBEGSIGN ADVANCE BEGIN OF VSYNC BY NVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NVBEGDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSBHO 1 0 ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 23. NTSC VSync Begin NVBEGDELO ...
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NVENDDELO NTSC VSync End Delay on Odd Field, Address 0xE6 [7] Table 114. NVENDDELO Function NVENDDELO Description 0 (default) No Delay. 1 Delay VSync going low on an odd field by a line relative to NVEND. NVENDDELE NTSC VSync End ...
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ADV7183A 622 623 624 625 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 310 311 312 313 OUTPUT VIDEO H V PVBEG[4: PFTOG[4:0] = 0x3 Figure 26. PAL Default (BT.656). The polarity of H, ...
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PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES PVBEGDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSBHO 1 0 ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 28. PAL VSync Begin PVBEGDELO PAL ...
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ADV7183A PVENDSIGN PAL VSync End Sign, Address 0xE9 [5] Table 129. PVENDSIGN Function PVENDSIGN Description 0 (default) Delay end of VSync. Set for user manual programming. 1 Advance end of VSync. Not recommended for user programming. PVEND[4:0] PAL VSync End, ...
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VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7183A: • Wide screen signaling (WSS) • Copy generation management systems (CGMS) • Closed captioning (CCAP) • EDTV • Gemstar 1×- and 2×-compatible data recovery ...
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ADV7183A Wide Screen Signaling Data WSS1[7:0], Address 0x91 [7:0], WSS2[7:0], Address 0x92 [7:0] Figure 31 shows the bit correspondence between the analog video waveform and the WSS1/WSS2 registers. WSS2[7:6] are undetermined and should be masked out by software. SEQUENCE 11.0µs ...
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CGMS Data Registers CGMS1[7:0], Address 0x96 [7:0], CGMS2[7:0], Address 0x97 [7:0], CGMS3[7:0], Address 0x98 [7:0] Figure 33 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked out by software. ...
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ADV7183A Letterbox Detection Incoming video signals may conform to different aspect ratios (16:9 wide screen of 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal WSS sequence ...
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GDECAD configures the way in which data is embedded in the video data stream. The recovered data is not available through I inserted into the horizontal blanking period of an ITU-R BT656-compatible data stream. The data format is intended ...
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ADV7183A Table 151. Data Byte Allocation Raw Information Bytes 2× Retrieved from the Video Line Notes • DID. The data identification value is 0x140 (10-bit value). Care has been taken that in ...
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Table 152. Gemstar 2× Data, Half-Byte Mode Byte D[9] D[ ...
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ADV7183A Table 155. Gemstar 1× Data, Full-Byte Mode Byte D[9] D[ ...
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PAL CCAP Data Half-Byte output mode is selected by setting CDECAD = 0, full- byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Table 158 and Table ...
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ADV7183A GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48 [7:0]; Address 0x49 [7:0] The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an ...
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Table 163. NTSC Line Enable Bits and Corresponding Line Numbering Line Number line[3:0] (ITU-R BT.470) Enable Bit 0 10 GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ ...
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ADV7183A PIXEL PORT CONFIGURATION The ADV7183A has a very flexible pixel port that can be con- figured in a variety of formats to accommodate downstream ICs. Table 167 and Table 168 summarize the various functions that the ADV7183A’s pins can ...
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MPU PORT DESCRIPTION 2 The ADV7183A supports a 2-wire (I C-compatible) serial inter- face. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7183A and the system I master controller. Each slave device is recognized by ...
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ADV7183A REGISTER ACCESSES The MPU can write to or read from all of the ADV7183A’s registers, except those registers that are read-only or write-only. The Subaddress register determines which register the next read or write operation accesses. All communications with ...
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I C CONTROL REGISTER MAP Table 170. Control Port Register Map Details Register Name Reset Value Input Control 0000 0000 Video Selection 1100 1000 Reserved 0000 0100 Output Control 0000 1100 Extended Output Control 0101 0101 Reserved 0000 0000 ...
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ADV7183A Table 171. Control Port Register Map Bit Details Register Name Bit 7 Bit 6 Input Control VID_SEL.3 VID_SEL.2 Video ENHSPLL Selection Reserved Output VBI_EN TOD Control Extended BT656-4 Output Control Reserved Reserved Autodetect AD_SEC525_EN AD_SECAM_EN Enable Contrast CON.7 CON.6 ...
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Register Name Bit 7 Bit 6 HSync HSB.7 HSB.6 Position Control 2 HSync HSE.7 HSE.6 Position Control 3 Polarity PHS NTSC Comb CTAPSN.1 CTAPSN.0 Control PAL Comb CTAPSP.1 CTAPSP.0 Control ADC Control Reserved Manual CKILLTHR.2 Window Control Reserved Gemstar Ctrl ...
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ADV7183A Register Name Bit 7 Bit 6 NTSC V Bit NVBEGDEL O NVBEGDEL E Begin NTSC V Bit NVENDDEL O NVENDDEL E End NTSC F Bit NFTOGDEL O NFTOGDEL E Toggle PAL V Bit PVBEGDEL O PVBEGDEL E Begin PAL ...
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I C REGISTER MAP DETAILS Grayed out sections mark the reset value of the register. Table 172. Register 0x00 Subaddress Register Bit Description 0x00 Input INSEL [3:0]. The INSEL bits allow the Control user to select an input channel ...
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ADV7183A Table 173. Register 0x01 Subaddress Register Bit Description 0x01 Video Reserved Selection ENVSPROC Reserved BETACAM ENHSPLL Reserved Bit Register Setting Set to default 0 Disable VSync processor 1 ...
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Table 174. Register 0x03 Subaddress Register Bit Description 0x03 Output SD_DUP_AV. Duplicates the AV codes Control from the Luma into the chroma path. Reserved. OF_SEL [3:0]. Allows the user to choose from a set of output formats. TOD. Three-State Output ...
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ADV7183A Table 175. Register 0x04 Subaddress Register Bit Description 0x04 Extended RANGE. Allows the user to select Output the range of output values. Can Control be BT656 compliant, or can fill the whole accessible number range. EN_SFL_PIN. BL_C_VBI. Blank Chroma ...
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Table 176. Registers 0x07 and 0x08 Subaddress Register Bit Description 0x07 Autodetect AD_PAL_EN. PAL B/G/I/H autodetect enable. Enable AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL 60 autodetect enable. AD_N443_EN. NTSC443 autodetect ...
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ADV7183A Table 177. Registers 0x09 to 0x0E Subaddress Register Bit Description 0x09 Reserved Reserved. (Saturation) 0x0A Brightness BRI[7:0]. This register controls the brightness of the video signal. 0x0B Hue HUE[7:0]. This register contains the value for the color hue adjustment. ...
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Table 178. Registers 0x0F to 0x11 Subaddress Register Bit Description 0x0F Power Reserved. Management PDBP. Power-down bit priority selects between PWRDN bit or PIN. Reserved. PWRDN. Power-down places the decoder in a full power- down mode. Reserved. RES. Chip Reset ...
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ADV7183A Table 179. Registers 0x12 and 0x13 Subaddress Register Bit Description 0x12 Status Register 2. STATUS_2[7:0]. Provides Read-Only. information about the internal status of the decoder. STATUS_2[5:0]. Reserved 0x13 Status Register 3. STATUS_3[7:0]. Provides Read-Only. information about the internal status ...
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Table 182. Register 0x17 Subaddress Register Bit Description 0x17 Shaping YSFM[4:0]. Selects Y Filter Shaping Filter mode Control when in CVBS only mode. Allows the user to select a wide range of low-pass and notch filters. If either auto mode ...
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ADV7183A Table 183. Registers 0x18 and 0x19 Subaddress Register Bit Description 0x18 Shaping WYSFM[4:0]. Wideband Y Shaping Filter mode allows Filter the user to select which Y shaping filter is used for the Y Control 2 component of Y/C, YPbPr, ...
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Table 184. Register 0x27 Subaddress Register Bit Description 0x27 Pixel LTA[1:0]. Luma timing adjust Delay allows the user to specify a Control timing difference between chroma and luma samples. Reserved. CTA[2:0]. Chroma timing adjust allows a specified timing difference between ...
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ADV7183A Table 185. Registers 0x2B and 0x2C Subaddress Register Bit Description 0x2B Misc Gain PW_UPD. Peak white update Control determines the rate of gain. Reserved. CKE. Color kill enable allows the color kill function to be switched on and off. ...
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Table 186. Registers 0x2D to 0x30 Subaddress Register Bit Description 0x2D Chroma CMG[11:8]. Chroma manual Gain gain can be used to program a Control 1 desired manual chroma gain. Reading back from this register in AGC mode gives the current ...
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ADV7183A Table 187. Register 0x31 Subaddress Register Bit Description 0x31 VS and Reserved. FIELD Control 1 HVSTIM. Selects where within a line of video the VS signal is asserted. NEWAVMODE. Sets the EAV/SAV mode. Reserved. Table 188. Registers 0x32 and ...
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Table 189. Registers 0x34 to 0x36 Subaddress Register Bit Description 0x34 HS Position Control 1 HSE[10:8]. HS end allows the positioning of the HS output within the video line. Reserved. HSB[10:8]. HS begin allows the positioning of the HS output ...
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ADV7183A Table 191. Register 0x38 Subaddress Register Bit Description 0x38 NTSC Comb YCMN[2:0]. Luma Control Comb Mode, NTSC. CCMN[2:0]. Chroma Comb Mode, NTSC. CTAPSN[1:0]. Chroma Comb Taps, NTSC. Bit Comments 0 0 ...
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Table 192. Registers 0x39 and 0x3A Subaddress Register Bit Description 0x39 PAL Comb YCMP[2:0]. Luma Comb Control mode, PAL. CCMP[2:0]. Chroma Comb mode, PAL. CTAPSP[1:0]. Chroma comb taps, PAL. 0x3A ADC Reserved Control PWRDN_ADC_2. Enables power-down of ADC2. PWRDN_ADC_1. Enables ...
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ADV7183A Table 193. Register 0x3D Subaddress Register Bit Description 0x3D Manual Reserved. Window CKILLTHR[2:0]. Reserved. Table 194. Registers 0x41 to 0x4C Subaddress Register Bit Description 0x41 Resample Reserved Control SFL_INV. Controls the behavior of the PAL switch bit. Reserved. GDECEL[15:0]. ...
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Table 195. Registers 0x4D to 0x50 Subaddress Register Bit Description 0x4D CTI DNR CTI_EN. CTI enable. Control 1 CTI_AB_EN. Enables the mixing of the transient improved chroma with the original signal. CTI_AB[1:0]. Controls the behavior of the alpha-blend circuitry. Reserved. ...
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ADV7183A Table 196. Register 0x51 Subaddress Register Bit Description 0x51 Lock CIL[2:0]. Count-into-lock Count determines the number of lines the system must remain in lock before showing a locked status. COL[2:0]. Count-out-of-lock determines the number of lines the system must ...
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Table 197. Registers 0x8F and 0x90 Subaddress Register Bit Description 0x8F Free Run Reserved Line LLC_PAD_SEL [2:0]. Enables Length 1 manual selection of clock for LLC1 pin. Reserved. 0x90 VBI Info WSSD. Screen signaling Read Mode detected. Details CCAPD. Closed ...
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ADV7183A Table 198. Registers 0x91 to 0x9D Subaddress Register Bit Description 0x91 WSS1[7:0] WSS1[7:0]. Wide screen signaling data. Read-only register. 0x92 WSS1[7:0]. Wide WSS2[7:0] screen signaling data. Read-only register 0x93 EDTV1[7:0]. EDTV1[7:0] EDTV data register. Read- only register. 0x94 EDTV2[7:0] ...
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Table 199. Register 0xB2 Subaddress Register Bit Description 0xB2 CRC Enable Reserved. Write Register CRC_ENABLE. Enable CRC checksum decoded from CGMS packet to validate CGMSD. Reserved. Table 200. Register 0xC3 Subaddress Register Bit Description 0xC3 ADC ADC0_SW[3:0]. Manual muxing SWITCH ...
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ADV7183A Table 201. Register 0xC4 Subaddress Register Bit Description 0xC4 ADC ADC2_SW[3:0]. Manual muxing SWITCH 2 control for ADC2. Reserved. ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. Bit Comments 0 ...
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Table 202. Registers 0xDC to 0xE4 Subaddress Register Bit Description 0xDC Letterbox Control 1 LB_TH [4:0]. Sets the threshold value that detects a black. Reserved. 0xDD Letterbox Control 2 LB_EL[3:0]. Programs the end line of the activity window for LB ...
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ADV7183A Table 203. Registers 0xE5 to 0xE7 Subaddress Register Bit Description 0xE5 NTSC V Bit NVBEG[4:0]. How many lines after l Begin to set V high. NVBEGSIGN. NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even ...
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Table 204. Registers 0xE8 to 0xEA Subaddress Register Bit Description 0xE8 PAL V Bit PVBEG[4:0]. How many lines after l Begin to set V high. PVBEGSIGN. PVBEGDELE. Delay V bit going high by one line relative to PVBEG (even field). ...
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ADV7183A PROGRAMMING EXAMPLES MODE 1—CVBS INPUT (COMPOSITE VIDEO ON AIN5) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15–P8. Table 205. Mode 1 CVBS Input Register Address Register Value 0x00 0x04 0x01 0x88 ...
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MODE 2—S-VIDEO INPUT (Y ON AIN1 AND C ON AIN4) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15–P8. Table 206. Mode 2 S-Video Input Register Address Register Value 0x00 0x06 0x01 0x88 0x2B 0xE2 0x3A 0x12 ...
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ADV7183A MODE 4—CVBS TUNER INPUT PAL ONLY ON AIN4 8-bit, ITU-R BT.656 output on P15–P8. Table 208. Mode 4 Tuner Input CVBS PAL Only Register Address Register Value 0x00 0x83 0x07 0x01 0x17 0x41 0x19 0xFA 0x2B 0xE2 0x3A 0x16 ...
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PCB LAYOUT RECOMMENDATIONS The ADV7183A is a high precision, high speed, mixed-signal device. To achieve the maximum performance from the part important to have a well laid-out PCB board. The following is a guide for designing a board ...
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ADV7183A Digital Inputs The digital inputs on the ADV7183A were designed to work with 3.3 V signals, and are not tolerant signals. Extra components are needed logic signals are required to be applied to ...
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TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7183A video decoder are shown in Figure 42 and Figure 43. AVDD_5V R43 BUFFER 0Ω R39 C93 C 4.7kΩ 100µF B FILTER Q6 R53 L10 56Ω 12µH E R38 R89 75Ω ...
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ADV7183A AGND DGND S-VIDEO ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS Y FILTER CIRCUIT ANTI-ALIAS Pr FILTER CIRCUIT ANTI-ALIAS Pb FILTER CIRCUIT ANTI-ALIAS CBVS FILTER CIRCUIT RECOMMENDED ANTI-ALIAS FILTER CIRCUIT IS SHOWN IN FIGURE 41 ON THE PREVIOUS PAGE. THIS ...
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... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range ADV7183AKST 0°C to 70°C ADV7183ABST –40°C to +85°C EVAL-ADV7183BEB The ADV7183A is a Pb-free environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface- mount soldering 255° ...
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ADV7183A NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...