ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet - Page 42

• Manufacturer Part Number: ADV7183AKST
• Description: IC VIDEO DECODER NTSC 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183AKST

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV7183A
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
•
•
•
HSB[10:0] HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]
The HS Begin and HS End registers allow the user to freely
position the HS output (pin) within the video line. The values
in HSB[10:0] and HSE[10:0] are measured in pixel units from
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF,00,00,XY (see Figure 20). HSB is set to
00000000010b, which is 2 LLC1 clock cycles from count[0].
Table 97. HSB Function
HSB[10:0]
0x002
HSE[10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]
The HS Begin and HS End registers allow the user to freely
position the HS output (pin) within the video line. The values
in HSB[10:0] and HSE[10:0] are measured in pixel units from
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
Table 100. HS Timing Parameters (see Figure 20)
Standard
NTSC
NTSC Square Pixel
PAL
1
Default.
Beginning of HS signal via HSB[10:0].
End of HS signal via HSE[10:0].
Polarity of HS using PHS.
PIXEL
LLC1
BUS
HS
ACTIVE
VIDEO
Description
The HS pulse starts after the HSB[10:0] pixel after
the falling edge of HS.
Cr
D
E
Y
FF
HS Begin Adjust
(HSB[10:0])
00000000010b
00000000010b
00000000010b
00
4 LLC1
EAV
00
HSE[10:0]
1
XY
80
10
HS End Adjust
(HSE[10:0])
00000000000b
00000000000b
00000000000b
HSB[10:0]
80
10
H BLANK
1
80
Rev. B | Page 42 of 104
Figure 20. HS Timing
10
C
HS to Active Video
(LLC1 Clock Cycles)
(C in Figure 20)
272
276
284
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF,00,00,XY (see Figure 20). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count[0].
Table 98. HSE Function
HSE[9:0]
000 (default)
Example
1.
2.
To move 20 LLC1s away from active video is equal to
subtracting 20 from 1716 and adding the result in binary to
both HSB[10:0] and HSE[10:0].
PHS Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
Table 99. PHS Function
PHS
0 (default)
1
FF
To shift the HS towards active video by 20 LLC1s, add 20
LLC1s to both HSB and HSE, that is, HSB[10:0] =
[00000010110], HSE[10:0] = [00000010100]
To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000]
(1696 is derived from the NTSC total number of pixels =
1716.)
E
00
SAV
1
00
XY
Description
HS active high.
HS active low.
Description
HS pulse ends after HSE[10:0] pixel after falling
edge of HS.
Cb
Active Video
Samples/Line
(D in Figure 20)
720Y + 720C = 1440
640Y + 640C = 1280
720Y + 720C = 1440
Y
Cr
ACTIVE VIDEO
Y
D
Cb
Y
Cr
Total LLC1
Clock Cycles
(E in Figure 20)
1716
1560
1728