Z0220112VEGR4078 Zilog, Z0220112VEGR4078 Datasheet - Page 34

• Manufacturer Part Number: Z0220112VEGR4078
• Description: IC MODEM 2400BPS DSP AFE 44-PLCC
• Manufacturer: Zilog

Specifications of Z0220112VEGR4078

• Data Format: V.21, V.22, V.23, Bell 103, Bell 212A
• Baud Rates: 2.4k
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interface RAM
Data Pump Interface RAM Access Method
PS000904-0107
Notes:
The interface RAM is used by the data pump for normal operations. All writes to
the interface RAM should be Read-Modify-Write, where only the bits that must be
changed are affected. All undocumented bits are reserved and must be left intact.
To write to the data pump RAM:
1. Write data to RAMDL & RAMDH.
RAMIE
RAMI
RXIE
TXIE
1. Data pump RAM reads or writes requires approximately 0.1
2. Data pump RAM writes take effect at different times, depending upon
3. Writing Reg4, for example, to set Reg4, bit 7 (TXIE) to 0 in an interrupt
RXI
TXI
msec to complete.
the location being written to. During data modes, writes typically take
effect at the end of the next baud period. During other modes of oper-
ation, writes take effect in 0.1 msec.
handler while waiting for the data pump to set Reg4, bit 1 (RAMRQ) to
0 in the background, may cause unwanted side effects. Setting Reg4,
bit 1 (RAMRQ) to 1 may cause the data pump to repeat the read/write
request if the data pump had just set Reg4, bit 1 (RAMRQ) to 0; how-
ever, setting Reg4, bit 1 (RAMRQ) to 0 may abort the RAM read/write
request.
Figure 9. Host Interrupt Circuit Diagram
V.22BIS Data Pump with Integrated AFE
HIRQ
30