SI3015-BS Silicon Laboratories Inc, SI3015-BS Datasheet - Page 30

• Manufacturer Part Number: SI3015-BS
• Description: IC ISOMODEM LINE-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Enhanced Global Direct Access Arrangementr

Specifications of SI3015-BS

• Package / Case: 16-SOIC (3.9mm Width)
• Data Format: V.90
• Interface: Serial
• Voltage - Supply: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Product: Modem Module
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Baud Rates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Si3038
SDATA_IN) to the transmit pin, which is looped
externally to the receive pin. To enable external analog
loopback, set L1B2:0 (L2B2:0) = 110. Both analog
loopback modes require power, which is typically
supplied by the loop current from TIP and RING.
Digital Interface
The ID pins configure the Si3024 as a primary or
secondary AC’97 device as shown in Table 21.
The following sections describe Si3024 operation.
Si3024 as Secondary Device
The Si3024 can operate as a secondary device, which
allows up to two Si3024s to exist on the AC link along
with a primary device. The primary device can be an
AC’97 Rev. 2.1-compatible codec or an Si3024
configured as the primary device. When configured as a
secondary device, the Si3024’s BIT_CLK becomes an
input and is used as the master clock.
Si3024 as Primary MC’97 Codec
The Si3024 can operate as a primary AC’97 Rev 2.1
compatible codec. However, when there is an audio
AC’97 codec present on the AC-link, the Si3024 should
be configured as a secondary codec, and the audio
AC’97 codec should be configured as the primary.
When the Si3024 is configured as a primary device,
clocking is derived from a 24.576 MHz crystal across
the XIN and XOUT pins. An external 24.576 MHz
Master Clock can also be applied to XIN.
Si3024 Connection to the Digital AC’97
controller
The Si3024 communicates with its companion AC’97
controller through a digital serial link called the AC-link.
All digital audio streams, optional modem line codec
streams,
communicated
interconnect. Figure 27 illustrates the breakout of the
connecting signals.
30
Table 21. Device ID Configuration
ID1
1
1
0
0
and
over
ID0
command/status
1
0
1
0
Device
Primary device
Secondary device #1
Secondary device #2
Factory Test
this
point-to-point
information
serial
Rev. 2.01
is
Clocking
The Si3024 derives its internal clock, when primary,
from the 24.576 MHz clock and drives a buffered and
divided down (1/2) clock to its digital companion
controller over AC-link through the BIT_CLK signal.
Clock jitter at the DACs and ADCs is a fundamental
impediment to high quality output, and the internally
generated clock provides the Si3024 with a clean clock
that is independent of the physical proximity of the
Si3024’s companion AC’97 controller.
The beginning of all audio sample packets, or Audio
Frames, transferred over AC-link is synchronized to the
rising edge of the SYNC signal. SYNC is driven by the
AC’97 controller. The AC’97 controller takes BIT_CLK
as an input and generates SYNC by dividing BIT_CLK
by 256 and applying some conditioning to tailor its duty
cycle. This yields a 48-kHz SYNC signal whose period
defines an audio frame. Data is transitioned on AC-link
on each rising edge of BIT_CLK, and subsequently
sampled on the receiving side of AC-link on each
immediately following falling edge of BIT_CLK.
Resetting Si3038 Chipset
There are three types of reset:
After signaling a reset to the Si3038 chipset, the AC’97
controller should not attempt to play or capture modem
data until it has sampled a Codec Ready indication from
the Si3038 chipset. See "AC-Link Audio Input Frame
(SDATA_IN)" on page 34.
Cold reset—Initializes all Si3038 logic (registers
included) to its default state. Initiated by bringing
RESET low at least 1 µs during a time when
BIT_CLK is inactive.
Warm reset—Leaves the register contents
unaltered. Initiated by bringing SYNC high for at
least 1 µs in the absence of BIT_CLK.
Register reset—Initializes only the registers to their
default states. Initiated by a write to register 3Ch.