SI3015-BS Silicon Laboratories Inc, SI3015-BS Datasheet - Page 35

• Manufacturer Part Number: SI3015-BS
• Description: IC ISOMODEM LINE-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Enhanced Global Direct Access Arrangementr

Specifications of SI3015-BS

• Package / Case: 16-SOIC (3.9mm Width)
• Data Format: V.90
• Interface: Serial
• Voltage - Supply: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Product: Modem Module
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Baud Rates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Ready bit). Each new bit position is presented to AC-link
on a rising edge of BIT_CLK and subsequently sampled
by the AC’97 controller on the following falling edge of
BIT_CLK. This sequence ensures that data transitions
and subsequent sample points for both incoming and
outgoing data streams are time aligned.
SDATA_IN’s composite stream is MSB justified (MSB
first) with all non-valid bit positions (for assigned and
unassigned time slots) padded with 0s by the Si3024.
SDATA_IN data is sampled on the falling edges of
BIT_CLK by the AC’97 controller.
Slot 1: Status Address Port
The Status Address Port monitors status for Si3024
functions including, but not limited to, line-side
configuration.
Audio input frame slot 1’s stream echoes the control
register index for historical reference and for the data to
be returned in slot 2. (Assuming that slots 1 and 2 have
been tagged “valid” by the Si3024 during slot 0).
Status Address Port bit assignments:
The first bit (MSB) generated by the Si3024 is always
padded with a 0. The following seven bit positions
communicate the associated control register address
and the trailing 12 bit positions are padded with 0s by
the Si3024.
Slot 2: Status Data Port
The Status Data Port delivers 16-bit control register
read data.
Bit(19)—Reserved (padded with 0)
Bit(18:12)—Control Register Index (Echo of register
index for which data is being returned)
Bit(11:2)—SLOTREQ bits, bit 9 for Line 1 and bit 4
for Line 2. (See "Variable Sample Rate Signaling
Protocol" on page 32 for more details.)
Bit(1,0)—Reserved (padded with 0s)
SDATA_IN
BIT_CLK
SYNC
End of previous
Audio Frame
Codec
Ready
12.228 MHz
slot(1)
("1" = Time slot contains valid PCM data)
slot(2)
Tag Phase
81.4 nS
Time Slot "Valid"
Bits
Figure 31. AC-Link Audio Input Frame
slot(12)
"0"
"0"
"0"
Rev. 2.01
19
Slot 1
Status Data Port bit assignments:
If Slot 2 is tagged invalid by the Si3024, then the entire
slot is padded with 0s by the Si3024.
Slot 5: Modem Line 1 ADC
Audio input frame slot 5 contains MSB-justified modem
ADC output data for phone line #1 (ID = 0 or 1). The
modem ADC output resolution is 16 bits.
The Si3038 ships out its ADC output data MSB first and
pads any trailing non-valid bit positions with 0s to fill out
its 20-bit time slot.
Slot 5 data is sent by the controller at a rate below the
48 kHz rate of the AC-Link. Therefore, “tags” are used
to mark when there is valid data in slot 5. The tag for
slot 5 is bit 10 in slot 0.
The tag for slot 5 (and slot 10) is dependent on the
current power state. Slot 5 is inhibited by the following:
Note that slot 5 is active when the DAA is on-hook in
order to pass ringer and caller-ID data.
Slot 10: Modem Line 2 ADC
Audio input frame for Line 2.
Slot 12: Modem GPIO Status
Slot 12 contains latency critical signals for the Si3014
and the GPIO of the Si3024. Slot 12 also reflects the
status of the link between the Si3024 and Si3014. See
Table 22.
Bit(19:4)—Control Register Read Data (padded with
0s if tagged invalid by the Si3024)
Bit(3:0)—Reserved (padded with 0s)
PRC/PRE bit is set (register 3E, bit 10/12); ADC is
powered down.
MLNK bit is set (register 56, bit 12); AC-Link halt is
impending.
(48 KHz)
0
20.8
µ
S
19
Slot 2
Data Phase
0
19
Slot 3
0
19
Si3038
Slot 12
0
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