AT42QT1110-AU Atmel, AT42QT1110-AU Datasheet
AT42QT1110-AU
Specifications of AT42QT1110-AU
AT42QT1110-AUTR
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AT42QT1110-AU Summary of contents
Page 1
... MLF RoHS compliant – 32-pin TQFP RoHS compliant • Signal Processing: – Self-calibration, auto drift compensation, noise filtering, AKS technology • Applications: – Consumer and industrial applications, such as TV, media player, etc ™ ) ™ QTouch 11-key Sensor IC AT42QT1110-MU AT42QT1110-AU 9520I–AT42–03/10 ...
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... Pinout and Schematic 1.1 Pinout Configuration SNS0K SNS1 SNS1K VDD VSS SNS2K SNS2 SNS3 AT42QT1110-MU/AT42QT1110- SNS8/DETECT2 2 23 SNS7/DETECT1 3 22 SNS7K/DETECT0 4 21 VSS QT1110 QT1110 5 20 SNS6 6 19 SNS6K 7 18 VDD 8 17 SCK 9520I–AT42–03/10 ...
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... SNS8K/DETECT3 26 SNS9/DETECT4 27 SNS9K/DETECT5 28 CHANGE 29 RESET 30 SNS10/DETECT6 31 SNS10K/SYNC 32 SNS0 I Input only O Output only, push-pull 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Type Comments I/O Sense Pin I/O Sense Pin I/O Sense Pin P Power P Supply Ground I/O Sense Pin I/O Sense Pin I/O Sense Pin I/O ...
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... Schematics Figure 1-1. Typical Circuit: 7 keys With Detect Outputs and No External Trigger AT42QT1110-MU/AT42QT1110-AU 4 9520I–AT42–03/10 ...
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... Figure 1-2. Typical Circuit: 11 Keys With No External Trigger Vunreg VREG 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU QT1110 5 ...
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... Re Figure • Section 3.1 on page • Section 3.2 on page • Section 3.5 on page • Section 3.3 on page AT42QT1110-MU/AT42QT1110-AU 6 QT1110 1-1, Figure 1-2 and Figure 1-3 check the following sections for component values capacitors (Cs0 – Cs10) 8: Sample resistors (Rs0 – Rs10) ...
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... Internal Hardware tests – check for hardware failures in the device’s internal memory. • Functional checks – confirm that the device is operating within expected parameters. See Section 4.10 on page 20 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU for more information. for more information. ™ ) capacitive sensor ® ...
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... LED terminals which are constantly connected to Vss or Vdd do not need further bypassing. 3.4 PCB Cleanliness Modern no-clean flux is generally compatible with capacitive sensing circuits. AT42QT1110-MU/AT42QT1110-AU 8 Section 6.8 on page CAUTION PCB is reworked to correct soldering faults relating to the QT1110 any associated traces or components, be sure that you fully understand the nature of the flux used during the rework process ...
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... Figure 3-1. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU for the power supply range. If the power supply fluctuates slowly Figure 1.3 on page 4 for suggested regulator manufacturers. Caution: A regulator IC shared with other logic can result in erratic operation and is not advised. A single ceramic 0.1 µ ...
Page 10
... SPI state machine. It will then interpret the next byte it receives as a fresh command. When the QT1110 SPI interface is receiving a new command, it returns the “Idle” status code (0x55) on MISO during the first byte exchange to indicate to the master that the correct state for receiving instructions. AT42QT1110-MU/AT42QT1110-AU 10 9520I–AT42–03/10 ...
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... With the exception of “Send Setups”, control commands normally require a single byte exchange, unless CRC checking is enabled, in which case a second byte must be transmitted by the host with the calculated CRC of the command byte. Figure 4-1. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU A. Section 5 on page Section 6 on page Section 7 on page Sleep Command – ...
Page 12
... Report Requests are sent by the Host to instruct the QT1110 to return status information. The host sends the appropiate “Report Request” command, then transmits Null bytes on MOSI while the QT1110 returns the report data on MISO. Figure 4-3. AT42QT1110-MU/AT42QT1110-AU 12 Sleep Command – CRC Enabled Host (Sends on MOSI) Command: 0x05 Response: 0x55 ( Idle” ...
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... For example, to set the “Positive Recalibration Delay” to 1920 ms, address 5 in the memory map is set to 12 (0x0C). This is done with the “Set” command for address 5 (command code 0x95), as shown in 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Figure 4-3 on page 12 shows the exchange that takes place to read the 2-byte “All All Keys Report – CRC Enabled ...
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... CRC byte. The sent data is not applied to the memory location until the CRC byte has been received and verified. Figure 4-6. AT42QT1110-MU/AT42QT1110-AU 14 Positive Recalibration Delay Set Instruction – CRC Disabled Host (Sends on MOSI) Command: 0x95 Response: 0x55 ( Idle” ...
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... With CRC Enabled, this exchange takes 4 bytes, with a command CRC transmitted by the host and a report CRC returned by the QT1110 (see Figure 4-8. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Positive Recalibration Delay Get Instruction – CRC Disabled Host (Sends on MOSI) Command: 0xD5 Response: 0x55 ( Idle” ...
Page 16
... Only two host commands are recognized under Quick SPI mode. These are shown in Table 4-2. Command Store to EEPROM Enable Full SPI CRC checking is not implemented in Quick SPI mode for host commands or return data. AT42QT1110-MU/AT42QT1110-AU 16 Device Status Report Format Description Bit 7 Counter Detect status, channels 0 – ...
Page 17
... The CHANGE pin is asserted (pulled low) when the detection status of a key – The CHANGE pin is pulled low when a key’s status changes and is only released 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU The SPI interface becomes active after the QT1110 has completed its startup sequence, taking approximately 160 ms after power on/reset. ...
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... The use of a timed trigger, and the cycle period to be used, is set in the Device Mode setup byte (see Section 7.4 on page AT42QT1110-MU/AT42QT1110-AU 18 pin remains low as long as there is a key in detect, regardless of communications. communications are required to release the CHANGE pin. ...
Page 19
... With the guard channel not enabled, all the keys work normally. Note: 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Section 7.4 on page If a key is already “in detect” when the guard channel becomes active, that key will remain in detect and the guard key will not activate until the active key goes out of detect ...
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... Similarly, the DI is applied to a key that is going out of detect: it must take 10 acquisitions where the signal has not exceeded its detect threshold before it is declared to leave touch. AT42QT1110-MU/AT42QT1110-AU 20 Guard Channel Example If a particular channel is unused, the threshold of that channel should be set prevent the incorrect reporting of the unused channel as being in an error state ...
Page 21
... Each key can be enabled for AKS processing via the AKS mask (see Keys outside the group of enabled keys may be in detect simultaneously. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU 26). Alternatively, a scope can be used to measure the entire burst, and then the burst Section 6.8 Section 7.11 on page 33) ...
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... The host must wait for at least 150 µs for the operation to be completed before communications can be re-established. 5.3 Calibrate All (0x03) This command initiates the recalibration of all sensor keys. The host must wait for at least 150 µs for the operation to be completed before communications can be re-established. AT42QT1110-MU/AT42QT1110-AU 22 Table 5-1 Control Commands Code Note 0x01 ...
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... The host must wait for at least 150 µs for the operation to be completed before communications can be re-established. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU If valid settings have not previously been stored in the device EEPROM, the QT1110 continues to operate under the default settings. Section 4.3 on page 17) ...
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... ERROR there are no keys in an error state least one key is in error state. KEY_NUM: the key number (0 to 10) of the key in detect (if there is only one), or the number of the first key to go into detection when there are more than one. AT42QT1110-MU/AT42QT1110-AU 24 Report Requests ...
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... EEPROM CRC (0xC3) This command returns a 1-byte CRC checksum for the setup data in EEPROM. 6.6 RAM CRC (0xC4) This command returns a 1-byte CRC checksum for the setup data in RAM. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Send All Keys Report Format Bit 7 Bit 6 Bit 5 Bit 4 ...
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... LBL lower burst limit is good lower burst limit has error. MBL maximum burst limit is good maximum burst limit has error. The maximum burst limit is fixed at 2048 pulses. AKS_EN AKS is disabled AKS is enabled. CAL normal calibrating. KEY_EN key is disabled key is enabled. AT42QT1110-MU/AT42QT1110-AU 26 Send All Keys Report Format Bit 7 Bit 6 Bit 5 ...
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... Byte 0 6.15 Firmware Version (0xCA) Returns 1 byte containing the firmware version. Table 6-12. Byte 0 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Reference for Key “k” Report Format Bit 7 Bit 6 Bit 5 DET_6 DET_5 Note: During “LED Detect Hold Time” or “LED Fade”, the report indicates the new state of the DETECT pin. For example, if the DETECT output is in “ ...
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... Key8 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) 28 Key9 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) 29 Key10 NegativeThreshold (NTHR)/Negative Hysterisis (NHYST) 30 Extend Pulse Time 31 Key0 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) AT42QT1110-MU/AT42QT1110-AU 28 Table 7-1. Note that there is a Set Command Get Command 0x90 0xD0 0x91 ...
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... SIGNAL: selects serial or parallel acquisition of keys signals serial parallel. SYNC: selects the trigger type when SYNC Pin is selected as the trigger to start key acquisition Level 1 = Edge 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU column in Table 7-1, followed by a byte of data. Section 4.1 on page Section 5.2 on page 22 for details ...
Page 30
... CRC: enables or disables CRC disable enable. When this option is enabled, each data exchange must have a CRC byte appended. When report or setup data is being returned by the QT1110, a 1-byte checksum is returned. The host should confirm that this checksum is correct and, if not, should request the report again. AT42QT1110-MU/AT42QT1110- (timed) 0 (7-key mode) ...
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... Generally this is compensated for by the drift, but the greater the difference the longer this will take. In order to speed up this correction, the positive threshold is used: if the positive threshold is exceeded, the QT1110 (that is, all keys) is recalibrated. 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU 0 (Key 0) 0 (disabled) 0 (data mode) ...
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... If a key signal is determined to be above the positive threshold, the QT1110 will wait for this delay and confirm that the error condition is still present before initiating a recalibration. PRD: the positive recalibration delay, in multiples of 160 ms. Note: Default value: AT42QT1110-MU/AT42QT1110- counts above reference) 2 (25% positive hysteresis) Positive Drift Compensation ...
Page 33
... Address IN_DETECTn: PWM to output when key n is “In Detect” (where n is 0–7). 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Lower Burst Limit Bit 7 Bit 6 Bit 5 Where a key has a signal of less than the LBL, a detection is not reported on that key. 18 AKS Mask Bit 7 Bit 6 Bit 5 ...
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... After the key touch is removed, the “Detect” output can be held at the “In-Detect” PWM signal for a time before returning to the “Out of Detect” PWM signal. This allows a reasonable length of time for an LED to be illuminated. The length of this time is controlled by the LED Detect Hold Time. Valid values are in multiples of 16 ms. Default value: AT42QT1110-MU/AT42QT1110-AU 34 PWM Values Value Meaning ...
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... Note that bit 7 is reserved and should be set to zero. Default LATCH_n value: 7.16 Addresses 19–29: Negative Threshold (NTHR)/Negative Hysteresis (NHYST) Table 7-16. Address 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU LED Fade/Key to LED Bit 7 Bit 6 Bit 5 FADE LED_6 LED_5 Section 7.12 on page 33). 0 (disabled) 1 (enabled) LED Latch ...
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... Default KEY_n_NTHR value: Default KEY_n_NHYST value: 7.17 Address 30: Extend Pulse Time Table 7-17. Address 30 HIGH_TIME: Number of µs to extend the high pulse time. LOW_TIME: Number of µs to extend the low pulse time. AT42QT1110-MU/AT42QT1110-AU 36 Negative Threshold/Negative Hysteresis (Continued) Bit 7 Bit 6 Bit 5 Bit 4 KEY_6_NTHR KEY_7_NTHR ...
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... When this time is exceeded, the QT1110 (that is, all keys) is recalibrated, taking this key (and any others which are in detect) out of detection. This delay is set in a multiple of 2560 ms. Note: Default KEY_n_NDRIFT value: Default KEY_n_NRD value: 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Negative Drift Compensation/Negative Recalibration Delay Bit 7 Bit 6 Bit 5 KEY_0_NDRIFT KEY_1_NDRIFT ...
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... Internal RST pull-up resistor 8.4 Timing Specifications Parameter Description T Burst duration BS Fc Burst center frequency Fm Burst modulation, percentage T Pulse width PW AT42QT1110-MU/AT42QT1110-AU 38 -0.5 to +6V ±10 mA -1.0V to (Vdd + 0.5) Volts 100,000 write cycles -40°C to +85°C -65°C to +150° 5.5V ± Min Typ Max – ...
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... Full SPI Mode Parameter Time between bytes Time between communications 8.5.3 Quick SPI Mode Parameter Time between bytes Time between communications 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU Specification 8-bit 1.5 MHz 333 ns 333 ns High Leading (falling) edge Trailing (rising) edge 1 µs Specification 150 µ ...
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... Description Threshold voltage low (Activate) V RST Threshold voltage high (Release) Reset Minimum length of Reset low 8.7 Internal Resonator Parameter Internal RC oscillator AT42QT1110-MU/AT42QT1110-AU 40 Signals on SPI Pins During the Exchange of a Data Byte SCK SAMPLE MOSI/MISO CHANGE MOSI PIN CHANGE MISO PIN SS MSB ...
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... Power Consumption 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU 41 ...
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... Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R AT42QT1110-MU/AT42QT1110- TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) SIDE VIEW ...
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... AT42QT1110-AU – 32-pin TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. ...
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... Marking 8.10.1 AT42QT1110-MU – 32-pin MLF Either of the following markings may be used. Abbreviation of Part Number: AT42 AT42QT1110-MU/AT42QT1110-AU 44 Pin Abbreviation of 1110 Part Number: 1110 AT42QT -MU 4R5 Program week code number 1-52 Code revision: where: 4.5 Released 2... then using the underscore A = 27... ...
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... AT42QT1110-AU – 32-pin TQFP Either of the following markings may be used. Abbreviation of Part Number: AT42 Abbreviation of Part Number: AT42 8.11 Part Number 8.12 Moisture Sensitivity Level (MSL) 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU 32 Pin QT1110 QT1110 4R5 32 Pin ATMEL QT1110 QT1110 4R5 DATE/LOT ...
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... CRC_val = 0; unsigned char setup_data[42 for < sizeof(setup_data); i++) { } return(CRC_val); } AT42QT1110-MU/AT42QT1110- (crc ^ data) & 0x01u; data >>= 1u; crc >>= 1u; if(fb) { crc ^= 0x8c; } 0xB2, 0x00, 0x38, 0x12, 0x06, 0x06, 0x12, 0x07, 0xFF, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x32, 0xFF, 0x00, 0x29, ...
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... Revision D – February 2009 Revision E – April 2009 Revision F – July 2009 Revision G – October 2009 Revision H – February 2010 Revision I – March 2010 9520I–AT42–03/10 AT42QT1110-MU/AT42QT1110-AU History Initial Release Updated for chip revision 2.1 Updated SPI specifications ...
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... LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’ ...