DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 29

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 20. Example I
A)
B)
C)
D)
TYPICAL I
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
EXAMPLE I
START
cycle. This can result in a whole page being worn out
over time by writing a single byte repeatedly. Writing
a page one byte at a time wears the EEPROM out
eight times faster than writing the entire page at
once. The device’s EEPROM write cycles are speci-
fied in the Nonvolatile Memory Characteristics table.
The specification shown is at the worst-case temper-
ature. It can handle approximately ten times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating
the EEPROM’s estimated lifetime.
Reading a single byte from a slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave, the master generates a START condition,
writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h
TO C8h AND C9h
TWO-BYTE READ
-READ C8h AND C9h
2
C WRITE TRANSACTION
2
MSB
C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
1
0
SFP+ Controller with Digital LDD Interface
1
ADDRESS*
SLAVE
2
______________________________________________________________________________________
0
C Timing
START
START
START
START
0
0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1
A2h
A2h
A2h
A2h
WRITE
READ/
LSB
R/W
SLAVE
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
ACK
MSB
1 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0
1 1 0 0 1 0 0 0
1 1 0 0 1 0 0 0
b7
BAh
BAh
C8h
C8h
b6
b5
REGISTER ADDRESS
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
b4
b3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
REPEATED
REPEATED
START
START
b2
00h
01h
The device features nine separate memory tables that
are internally organized into 8-byte rows.
The Lower Memory is addressed from 00h–7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table-select byte.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as alarm and warning-enable
bytes.
Table 02h is a multifunction space that contains config-
uration registers, scaling and offset values, passwords,
interrupt registers as well as other miscellaneous con-
trol bytes.
Table 04h contains a temperature-indexed LUT for
control of the modulation voltage. The modulation LUT
can be programmed in 2°C increments over the -40°C
to +102°C range.
b1
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated
START condition, writes the slave address byte (R/W
= 1), reads data with ACK or NACK as applicable,
and generates a STOP condition.
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
LSB
SLAVE
SLAVE
b0
ACK
ACK
A3h
A3h
SLAVE
ACK
0 1 1 1 0 1 0 1
STOP
75h
SLAVE
SLAVE
ACK
ACK
MSB
b7
b6
DATA IN BAh
DATA IN C8h
SLAVE
ACK
DATA
DATA
b5
Memory Organization
STOP
b4
DATA
MASTER
MASTER
b3
NACK
ACK
b2
STOP
DATA IN C9h
b1
DATA
LSB
b0
SLAVE
ACK
MASTER
NACK
STOP
STOP
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