DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 56

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DS1878T+T&R

Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet

Specifications of DS1878T+T&R

Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 01h, Register FEh–FFh: RESERVED
SFP+ Controller with Digital LDD Interface
Table 01h, Register FDh: WARN EN
56
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F9h
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
MEMORY TYPE
Layout is identical to WARN
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
MEMORY TYPE
These registers are reserved.
MON3 HI
BITS 3:0
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
MON3 HI:
0 = Disables interrupt from MON3 HI warning.
1 = Enables interrupt from MON3 HI warning.
MON3 LO:
0 = Disables interrupt from MON3 LO warning.
1 = Enables interrupt from MON3 LO warning.
MON4 HI:
0 = Disables interrupt from MON4 HI warning.
1 = Enables interrupt from MON4 HI warning.
MON4 LO:
0 = Disables interrupt from MON4 LO warning.
1 = Enables interrupt from MON4 LO warning.
RESERVED
MON3 LO
2
2
00h
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
PW2 or (PW1 and RWTBL1C)
Nonvolatile (SEE)
in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory,
MON4 HI
00h
N/A
N/A
Nonvolatile (SEE)
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED
BIT 0

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