AD9847AKST Analog Devices Inc, AD9847AKST Datasheet
AD9847AKST
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AD9847AKST Summary of contents
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FEATURES Correlated Double Sampler (CDS) – +10 dB Pixel Gain Amplifier ( PxGA 10-Bit Variable Gain Amplifier (VGA) 10-Bit 40 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip ...
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AD9847 –SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE Analog (AVDD1 Digital1 (DVDD1) H1–H4 Digital2 (DVDD2) RG Digital3 (DVDD3) D0–D11 Digital4 (DVDD4) All Other Digital POWER DISSIPATION DVDD1 (@ 5 V, 100 ...
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ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient* Max Input Range before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (32) Med ...
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AD9847 TIMING SPECIFICATIONS Parameter MASTER CLOCK (CLI) CLI Clock Period CLI High/Low Pulsewidth Delay from CLI to Internal Pixel Period Position EXTERNAL MODE CLAMPING CLPDM Pulsewidth CLPOB Pulsewidth* SAMPLE CLOCKS SHP Rising Edge to SHD Rising Edge DATA OUTPUTS Output ...
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... BYP1–3, CCDIN to AVSS . . . . . . . . –0.3 to AVDD + 0.3 V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Temperature (10 sec 300°C Model AD9847AKST CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9847 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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AD9847 Pin No. Mnemonic Type* 1–5 D0– DVSS3 P 7 DVDD3 P 8–12 D5–D9 DO 13 DVSS1 P 16 DVDD1 P 17 DVSS2 ...
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Equivalent Input/Output Circuits AVDD2 R AVSS2 Circuit 1. CCDIN (Pin 29) AVDD1 330 25k CLI 1.4V AVSS1 Circuit 2. CLI (Pin 23) DVDD4 DATA THREE- STATE DVSS4 Circuit 3. Data Outputs D0–D9 (Pins 1–5, 8–12) Typical Performance Characteristics 0.50 0.25 ...
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AD9847 SYSTEM OVERVIEW Figures 1a and 1b show the typical system application diagrams for the AD9847. The CCD output is processed by the AD9847’s AFE circuitry, which consists of a CDS, PxGA, VGA, black level clamp, and A/D converter. The ...
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SERIAL INTERFACE TIMING SDATA SCK NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS. 3. FOR ...
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AD9847 Accessing a Double-Wide Register There are many double-wide registers in the AD9847, e.g., oprmode, clpdmtog1_0, and clpdmscp3, and so on. These regis- ters are configured into two consecutive 6-bit registers with the least significant six bits located in the ...
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Bit Default Address Content Width Value CLPDM # Bits 146 [5: [5: [5: [5: [0] ...
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AD9847 Bit Default Address Content Width Value CLPOB # Bits 146 [5: [5: [5: [5: ...
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Bit Default Address Content Width Value HBLK # Bits 147 [5: [5: [5: [5:0] ...
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AD9847 Bit Default Address Content Width Value PBLK # Bits 146 [5: [5: [5: [5: ...
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Bit Address Content Width AFE Register Breakdown oprmode [7:0] [1:0] 2'h0 2'h1 2'h2 2'h3 [2] [3] [4] [5] [6] [7] ctlmode [5:0] [2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 [3] [4] 1'h0 1'h1 [5] 1'h0 1'h1 PRECISION TIMING ...
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AD9847 High Speed Clock Programmability Figure 5 shows how the high speed clocks RG, H1–H4, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges and may be inverted using the polarity control. The horizontal clocks ...
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P[0] POSITION PIXEL PERIOD RGr[0] RG Hr[0] H1/H3 CCD SIGNAL NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE. Figure 6. High ...
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AD9847 HORIZONTAL CLAMPING AND BLANKING The AD9847’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal and are then organized into multiple ...
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HD HBLK H1/H3 H1/H3 H2/H4 Horizontal Sequence Control The AD9847 uses sequence change positions (SCP) and sequence pointers (SPTR) to organize the individual horizontal sequences four SCPs are available to divide the readout into four separate regions, as ...
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AD9847 H-Counter Synchronization The H-Counter reset occurs on the sixth CLI rising edge following the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter (see Figure 13). POWER-UP PROCEDURE Recommended Power-Up Sequence When the ...
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ANALOG FRONT END DESCRIPTION AND OPERATION The AD9847 signal processing chain is shown in Figure 15. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. DC Restore To reduce the large dc ...
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AD9847 FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN ...
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FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER, STEERING BETWEEN “012012” ...
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AD9847 VD COLOR 3 PxGA STEERING HD STEERING CONTROL SHP/SHD 2 GAIN0 GAIN1 4:1 MUX GAIN2 GAIN3 6 PxGA CDS VGA Figure 17. PxGA Block Diagram CCD: PROGRESSIVE BAYER MOSAIC SEPARATE COLOR STEERING MODE LINE0 GAIN0, ...
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Optical Black Clamp The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ...
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AD9847 CCDIN 29 AD9847 SIGNAL OUT CCD IMAGER Figure 22a. CCD Connections (2 H-Clock) AD9847 SIGNAL H1 ...
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Timing Examples (continued) CCDIN INVALID PIXELS VERT SHIFT DUMMY SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY CCDIN SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY ...
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AD9847 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW Revision History Location 1/03—Data Sheet changed from REV REV. A. Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . ...