AD9847AKST Analog Devices Inc, AD9847AKST Datasheet - Page 21

• Manufacturer Part Number: AD9847AKST
• Description: IC CCD SIGNAL PROC 10BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9847AKST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 40MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7/3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

REV. A
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9847 signal processing chain is shown in Figure 15.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a
dc-restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V analog supply of the
AD9847.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the video
information and reject low frequency noise. The timing shown
in Figure 6 illustrates how the two internally generated CDS
clocks, SHP and SHD, are used to sample the reference level and
data level of the CCD signal, respectively. The placement of the
SHP and SHD sampling edges is determined by the setting of
the SHPPOSLOC and SHDPOSLOC registers located at
Addresses 0xF0 and 0xF1, respectively. Placement of these two
clock signals is critical in achieving the best performance from
the CCD.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. The AD9847 removes this offset in the input
stage to minimize the effect of a gain change on the system black
level, usually called the “gain step.”
0.1 F
0.1 F
0.1 F
0.1 F
CCDIN
BYP1
BYP 2
BYP 3
DC RESTORE
1.5V
SHP
CDS
SHD
INPUT OFFSET
CLAMP
CLPDM
Figure 15. Analog Front End Block Diagram
–2dB TO +10dB
PxGA
SHP SHD
GENERATION
PRECISION
TIMING
REGISTER
VGA GAIN
0dB TO 36dB
VGA
PHASE
DOUT
10
–21–
INTERNAL
BIASING
Another advantage of removing this offset at the input stage is to
maximize system headroom. Some area CCDs have large black
level offset voltages, which, if not corrected at the input stage, can
significantly reduce the available headroom in the internal circuitry
when higher VGA gain settings are used.
Horizontal timing examples are shown on the last page of the
Applications Information section. It is recommended that the
CLPDM pulse be used during valid CCD dark pixels. CLPDM
may be used during the optical black pixels, either together with
CLPOB or separately. The CLPDM pulse should be a minimum
of four pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to “multiplex” its gain value
on a pixel-to-pixel basis (see Figure 17). This allows lower out-
put color pixels to be gained up to match higher output color
pixels. Also, the PxGA may be used to adjust the colors for white
balance, reducing the amount of digital processing that is needed.
The four different gain values are switched according to the
Color Steering circuitry. Seven different color steering modes
for different types of CCD color filter arrays are programmed
in the AD9847 AFE Register, ctlmode, at Address 0x06
(see Figures 16a to 16g for timing examples). For example,
Mosaic Separate steering mode accommodates the popular
“Bayer” arrangement of red, green, and blue filters (see Figure 18).
CLPDM CLPOB PBLK
8-BIT
DAC
GENERATION
TIMING
0.1 F
CML
V-H
AVDD
DIGITAL
FILTER
2
OPTICAL BLACK
INTERNAL
REFB
1.0V
CLAMP
1.0 F
10-BIT
ADC
V
REF
2V FULL SCALE
1.0 F
2.0V
REFT
CLAMP LEVEL
REGISTER
8
CLPOB
AD9847
OUTPUT
LATCH
DATA
PBLK
PHASE
DOUT
10
AD9847
DOUT