AD8174ARZ Analog Devices Inc, AD8174ARZ Datasheet - Page 8

• Manufacturer Part Number: AD8174ARZ
• Description: IC MUX SWITCHNG W/AMP 4:1 14SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8174ARZ

• Applications: Multiplexer with Amplifier
• Voltage - Supply: ±4 V ~ 6 V
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Mounting Type: Surface Mount
• No. Of Circuits: 4
• Supply Current: 9.7mA
• Supply Voltage Range: ± 4V To ± 6V
• Operating Temperature Range: -40°C To +85°C
• Analog Switch Case Style: SOIC
• No. Of Pins: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8170/AD8174
THEORY OF OPERATION
General
The AD8170/AD8174 multiplexers integrate wideband analog
switches with a high speed current feedback amplifier. The
input switches are complementary bipolar follower stages that
are turned on and off by using a current steering technique that
attains switch times of less than 10 ns and ensures low switching
transients. The 250 MHz current feedback amplifier provides
up to 50 mA of drive current. Overall gain and frequency
response are set by external resistors for maximum versatility.
Figure 22 is a block diagram of the multiplexer signal chain,
with a simplified schematic of an input switch. When the
channel is on (i.e., V
negative than V
through Q3 and Q4. This biases up Q5 through Q8 to form the
unity gain follower. I1 and I4 (the “off” currents) are steered,
either to another switch or to the power supply. When the
channel turns off, I2 and I3 are steered away while I1 switches
over to pull the base of Q8 up to V
from ground reference) and I4 switches over to pull the base of
Q5 down to V
reference). Clamping the bases of the reverse biased output
transistors to a low impedance point greatly improves isolation
performance.
The AD8174 has four switches with outputs wired together and
driving the positive input of a current feedback amplifier to form
a 4:1 multiplexer. It is designed so that only one channel is on
at a time. By bringing ENABLE high, the supply current for the
amplifier is shut off. This turns the output of the amplifier into
a high impedance, allowing the AD8174 to be used in larger
arrays. In practice, the disabled output impedance of the mux
will be determined by the amplifier’s feedback network.
V
EN
CLB
(OUT )
REFT
VCLT
– 1 V
nV / Hz
), I2 flows through Q1 and Q2, and I3 flows
ONB
BE
more positive than V
(about –2.7 volts away from ground
VREFT
VREFB
Figure 22. Block Diagram and Simplified Schematic of the AD8170
CLT
I
EN
+ 1 V
I1
I2
R
S
BE
VONB
VOFFT
IN3
REFB
2
(about 2.7 volts
V
V
, V
EN
Q2
EN
Q1
VREFT
VREFB
ONT
p p
2
more
1
V
R
R
IN0
IN1
IN2
G
EN
F
–8–
2
I3
I4
I
Bringing SD high shuts off the supply current for all the switches,
that some of the logic control circuitry and the amplifier,
reducing the quiescent current drain to 1.5 mA. If the
ENABLE and SD functions are not to be used, those respective
pins must be tied to ground for proper operation. Any unused
channel input should also be tied to ground.
The AD8170 has two switches driving an amplifier to form a 2:1
multiplexer. No disable or shutdown functions are provided.
DC Performance and Noise Considerations
Figure 23 shows the different contributors to total output offset
and noise. Total expected output offset can be calculated using
Equation 1 below:
Equations 2 and 3 below can be used to predict the output
voltage noise of the multiplexer for different choices of gains
and external resistors. The different contributions to output
noise are root-sum-squared to calculate total output noise
spectral density in Equation 2. As there is no peaking in the
multiplier’s noise characteristic, the total peak-to-peak output
noise will be accurately predicted using Equation 3.
f
EN
VOFFB
3 dB
VONT
–
R
V
6.2 1.26
Figure 23. DC Errors for Buffered Multiplexer
Q3
Q4
V
F
OS
IN
2
out
4KT R
R
VCLB
S
I
B
F
I
B
+
/I
en
R
R
Q6
Q5
Q7
Q8
+
SWITCH
S
S
V
1
OS
V
/V
R
R
OS
en
G
F
2
1
R
R
R
I
B
I6
G
–
G
F
/I
BUFFER
en
R
R
VOUT
–
G
F
VFB
I
2
B
R
R
R
F
G
F
V
OUT
REV. 0
(3)
(2)
(1)