HCTL-2032-SC Avago Technologies US Inc., HCTL-2032-SC Datasheet - Page 13

• Manufacturer Part Number: HCTL-2032-SC
• Description: IC DECODER/COUNTER 32BIT 32-SOIC
• Manufacturer: Avago Technologies US Inc.
• Type: Quadrature Decoder/Counter Interface ICr

Specifications of HCTL-2032-SC

• Package / Case: 32-SOIC (7.5mm Width)
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1885-5; HCTL-2032-SC

3
Digital Noise Filter
The digital noise filter section is responsible for rejecting
noise on the incoming quadrature signals. The input sec-
tion uses two techniques to implement improved noise
rejection. Schmitt-trigger inputs and a three-clock-cycle
delay filter combine to reject low level noise and large,
short duration noise spikes that typically occur in mo-
tor system applications. Both common mode and dif-
ferential mode noise are rejected. The user benefits from
these techniques by improved integrity of the data in the
counter. False counts triggered by noise are avoided.
Figure 11 shows the simplified schematic of the input sec-
tion. The signals are first passed through a Schmitt-trig-
ger buffer to address the problem of input signals with
Figure 11. Simplified Digital Noise Filter Logic
CK
CK
CK
CHA
CHB
CHI
D
D
D
Q
Q
Q
D
D
D
Q
Q
Q
D
D
D
Q
Q
Q
D
D
D
slow rise times and low-level noise (approximately < 1V).
The cleaned up signals are then passed to a four-bit delay
filter. The signals on each channel are sampled on rising
clock edges. A time history of the signals is stored in the
four-bit shift register. Any change on the input is tested
for a stable level being present for three consecutive ris-
ing clock edges. Therefore, the filtered output waveforms
can change only after an input level has the same value
for three consecutive rising clock edges.
Refer to Figure 12, which shows the timing diagram. The
result of this circuitry is that short noise spikes between
rising clock edges are ignored and pulses shorter than
two clock periods are rejected.
Q
Q
Q
CK
CK
CK
J
K
J
K
J
K
Q
Q
Q
filtered
filtered
filtered
CHA
CHB
CHI