W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet
W83627DHG
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W83627DHG Summary of contents
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... WINBOND LPC I/O Note: This document is for UBC, UBE and UBF version except specified descriptions Date : April 10, 2007 Version : 1.4 W83627DHG ...
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...
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... Remove the note and renew the descriptions for Index# of FDC Interface. 2. Correct the descriptions of HM Device Bank 0, CR[12h] N.A. bit0. 3. Add two control CPUFAOUT1 output type selection. 4. Add a new bit at LDC, CR[E8h] bit 1 for more PECI Publication Release Date: Aug, 22, 2007 -I- W83627DHG bits for AUXFANOUT and Version 1.4 ...
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... Add new chapters for Serial Peripheral Interface, Configuration Register Management, Serialized IRQ, Watchdog Timer VID Inputs and Outputs, and PCI Reset Buffers. 2. Update the feature lists of the W83627DHG in Chapter 2 Features. 3. Add descriptions of PECI and SST and a table of SMBus in Chapter 5 Pin Description. 4. ...
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... Add a new DC spec. of RSMRST# PWROK for UBF version (In section 14.3 and 14.4) N.A. 2. Add LPC Timing in section 21.4 3. Remove redundant Power on/off and LRESET# Timing N.A. 1. Modify LPC Timing in section 21.4 Publication Release Date: Aug, 22, 2007 -III- W83627DHG – VSBGATE#, ATXPGD, Version 1.4 ...
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... Software Programming Example ...........................................................................................26 7. HARDWARE MONITOR ................................................................................................................. 28 7.1 General Description .............................................................................................................. 28 7.2 Access Interfaces.................................................................................................................. 28 7.2.1 LPC Interface .........................................................................................................................29 2 7.2 interface ...........................................................................................................................30 7.3 Analog Inputs ........................................................................................................................ 31 7.3.1 Voltages Over 2.048 V or Less Than 0 V...............................................................................31 7.3.2 Voltage Detection...................................................................................................................32 W83627DHG Publication Release Date: Aug, 22, 2007 -IV- Version 1.4 ...
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... Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0).............. 69 8.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0) ..................................................... 69 8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0)................................................ 70 Control ..........................................................................................................41 -V- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0) ....................................... 91 8.64 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0)............................... 92 8.65 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0)....................................... 92 8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0) ....................................... 93 W83627DHG Publication Release Date: Aug, 22, 2007 -VI- Version 1.4 ...
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... Using the SPI Interface via the LPC ................................................................................... 108 10. FLOPPY DISK CONTROLLER..................................................................................................... 111 10.1 FDC Functional Description ................................................................................................ 111 10.1.1 FIFO (Data)..........................................................................................................................111 10.1.2 Data Separator.....................................................................................................................112 10.1.3 Write Precompensation........................................................................................................112 10.1.4 Perpendicular Recording Mode............................................................................................112 10.1.5 FDC Core.............................................................................................................................112 W83627DHG Publication Release Date: Aug, 22, 2007 -VII- Version 1.4 ...
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... CFIFO (Parallel Port Data FIFO) Mode = 010......................................................................153 12.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011 ..........................................................................153 12.3.7 TFIFO (Test FIFO Mode) Mode = 110 .................................................................................154 12.3.8 CNFGA (Configuration Register A) Mode = 111 ..................................................................154 12.3.9 CNFGB (Configuration Register B) Mode = 111 ..................................................................154 W83627DHG Publication Release Date: Aug, 22, 2007 -VIII- Version 1.4 ...
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... Chip (Global) Control Register ............................................................................................ 180 20.2 Logical Device 0 (FDC) ....................................................................................................... 187 20.3 Logical Device 1 (Parallel Port)........................................................................................... 190 20.4 Logical Device 2 (UART A) ................................................................................................. 191 20.5 Logical Device 3 (UART B) ................................................................................................. 191 20.6 Logical Device 5 (Keyboard Controller) .............................................................................. 193 W83627DHG Publication Release Date: Aug, 22, 2007 -IX- Version 1.4 ...
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... UART/Parallel Port...............................................................................................................236 21.3.9 Parallel Port Mode Parameters ............................................................................................238 21.3.10 Parallel Port .........................................................................................................................239 21.3.11 KBC Timing Parameters ......................................................................................................248 21.3.12 GPIO Timing Parameters.....................................................................................................251 21.4 LPC Timing.......................................................................................................................... 253 22. TOP MARKING SPECIFICATION ................................................................................................ 254 23. PACKAGE SPECIFICATION ........................................................................................................ 255 W83627DHG Publication Release Date: Aug, 22, 2007 -X- Version 1.4 ...
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... III, which makes the system more stable and user-friendly. AN The W83627DHG supports four -- 360K, 720K, 1.2M, 1.44M, or 2.88M -- disk drive types and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The disk drive adapter supports the functions of floppy disk drive controller (compatible with the industry standard 82077/ 765), data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic ...
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... Break, parity, overrun, framing error simulation Programmable baud rate generator allows division of clock source by any value from Maximum baud rate for clock source 14.769 MHz 921K bps. The baud rate at 24 MHz is 1.5 M bps. W83627DHG Publication Release Date: Aug, 22, 2007 -2- 16 -1) Version 1 ...
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... Eight VID inputs / outputs 2 Provide I C interface to read / write registers Serial Peripheral Interface Support bits SPI Flash Memory with clock MHz Support Mode 0 and Mode 3 MART TM F III MART AN TM mode TM support -3- W83627DHG “Thermal Cruise AN Publication Release Date: Aug, 22, 2007 Version 1.4 ” and ...
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... Simple Serial Transport™ Interface SST temperature and voltage Combination Sensor command support Support SST 0.9 Specification PECI Interface Support PECI 1.0 Specification Support 4 CPU addresses and 2 domains per CPU address Package 128-pin QFP Pb-free/RoHS W83627DHG Publication Release Date: Aug, 22, 2007 -4- Version 1.4 ...
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... VID I/O pins Serial Peripheral Interface LPC Interface UARTA UARTB GPIO HM KBC ACPI VID Interface SPI W83627DHG -5- W83627DHG Floppy drive FDC interface signals UARTA interface signals UARTB interface signals Infrared interface IR signals Printer port PRT interface signals PECI PECI Publication Release Date: Aug, 22, 2007 ...
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... VID3 VID3 125 125 VID2 VID2 126 126 VID1 VID1 127 127 VID0 VID0 128 128 Pin Layout for W83627DHG UBC version 3VSB 3VSB VBAT VBAT W83627DHG W83627DHG 3VCC 3VCC Publication Release Date: Aug, 22, 2007 -6- W83627DHG 64 64 3VSB 3VSB GP37 ...
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... GP20/CPUFANOUT1 120 VID7 121 VID6 122 VID5 123 VID4 124 VID3 125 VID2 126 VID1 127 VID0 128 Pin Layout for W83627DHG UBE and UBF version 3VSB 3VSB VBAT W83627DHG 3VCC Publication Release Date: Aug, 22, 2007 -7- W83627DHG 64 GP37/SUSC# 63 KDAT/GP26 62 KCLK/GP27 61 3VSB 60 ...
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... TTL-level output pin with 24-mA source-sink capability Open-drain output pin with 8-mA sink capability Open-drain output pin with 12-mA sink capability Open-drain output pin with 24-mA sink capability 24 I/O - Bi-direction pin with source capability and sink capability W83627DHG Publication Release Date: Aug, 22, 2007 -8- Version 1.4 ...
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... LPC bus between a host and a peripheral. Indicates the start of a new cycle or the termination of a broken cycle. Reset signal. It can be connected to the PCIRST# signal on the host. DESCRIPTION This active-low open-drain output produces a -9- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... ECP and EPP modes. PRINTER MODE: SLIN# Output line for detection of printer selection. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. -10- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Parallel port data bus bit 6. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD7 Parallel port data bus bit 7. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. -11- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... I/O port′s configuration address. General-purpose I/O port 6 bit 5. Data Set Ready. An active-low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General-purpose I/O port 6 bit 6. Publication Release Date: Aug, 22, 2007 -12- W83627DHG Version 1.4 ...
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... General-purpose I/O port 4 bit 2. Note: This pin changes to input state during internal PWROK from low to high, then goes back to the previous setting state. (Please see the AP Note 1 of W83627DHG) Serial Input. This pin is used to receive serial data through the communication link. ...
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... To initiate the data transfer between the W83627DHG and a slave device, SCE# must go low. This synchronizes the slave device with the W83627DHG. Data can now be transferred between the W83627DHG and the slave device in one of two modes: the data is sampled either on the rising or the falling edge of the clock. ...
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... Transfer commands, address or data to serial flash. This pin is 8 connected serial flash. CASE OPEN detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627DHG is t turned off. Pulling up a 2-MΩ resistor to VBAT is recommended if not in use. ...
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... Determines the initial FAN speed. Power on configuration for 2 fan speeds, 50% or 100%. During power-on reset, this pin is pulled td down internally and the fan speed is 50%. Only CPUFANOUT0 is supported. Power LED output. Drive high 3.3 V after strapping. 12 -16- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... ACPI supports the functions of thermal management, state management, and speed control, as well as the global system states and different device power states. Two of the primary states that the W83627DHG supports are the S0 (working) and S3 (suspend to RAM) states full-power state, in which the computer is actively used sleeping state, in which the processor is powered down, but the memory, where the last procedural state is stored, is still active ...
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... PCI Reset Buffer 2. (Default) General-purpose I/O port 3 bit 2. 12t Serial Bus clock. PCI Reset Buffer 3. (Default) General-purpose I/O port 3 bit 3. 12t Serial bus bi-directional Data. -18- W83627DHG POWER SOURCE 3VCC 3VSB 3VSB 3VSB 3VSB 3VCC Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... General-purpose I/O port 2 bit 4. 16t PS2 Mouse Data. 16ts General-purpose I/O port 2 bit 5. 16t PS2 Mouse Clock. 16ts General-purpose I/O port 2 bit 6. 16t Keyboard Data. 16ts General-purpose I/O port 2 bit 7. 16t Keyboard Clock. 16ts -19- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... UBE and UBF version only) General-purpose I/O port 3 bit 7. SLP_S5# input. (This pin function is both for UBE and UBF version only) Publication Release Date: Aug, 22, 2007 -20- W83627DHG Version 1.4 ...
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... Suspended LED output. General-purpose I/O port 5 bit 6. Panel Switch Input. This pin is active-low with an internal pulled-up resistor. General-purpose I/O port 5 bit 7. Panel Switch Output. This signal is used to wake-up the system from S3/S5 state. Publication Release Date: Aug, 22, 2007 -21- W83627DHG Version 1.4 ...
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... Connect to the reset button. This pin has internal de-bounce IN circuit whose de-bounce time is at least 32 mS. (This pin t function is both for UBE and UBF version only) General-purpose I/O port 3 bit 6. 12 -22- W83627DHG DESCRIPTION and a 1-kΩ resistor Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... V power supply for driving host interface. Analog +3.3 V power input. Internally supply power to all analog circuits. Analog ground. The ground reference for all analog input. Internally connected to all analog circuits. Ground. ® INTEL CPU Vtt power. Publication Release Date: Aug, 22, 2007 -23- W83627DHG Version 1.4 ...
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... CONFIGURATION REGISTER ACCESS PROTOCOL The W83627DHG uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627DHG has totally twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of Logical Device 4 for backward compatibility) corresponding to twelve individual functions: FDC (Logical Device 0), Parallel Port (Logical Device 1), UARTA (Logical Device 2), UARTB (Logical Device 3), Keyboard Controller (Logical Device 5), SPI (Serial Peripheral Interface, Logical Device 6), GPIO6 (Logical Device 7), WDTO# & ...
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... Check Pass key Check Pass key N N Extended Function Extended Function To program the W83627DHG configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode. 6.1.1 Enter the Extended Function Mode To place the chip into the Extended Function Mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers (EFERs, i ...
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... MOV AL, 01H OUT DX select Logical Device 1 ; MOV DX, 2EH MOV AL, F0H OUT DX select CRF0 MOV DX, 2FH MOV AL, 3CH OUT DX update CRF0 with value 3CH ;---------------------------------------------------------------------------- ; Exit the Extended Function Mode ;---------------------------------------------------------------------------- MOV DX, 2EH MOV AL, AAH OUT DX, AL W83627DHG Publication Release Date: Aug, 22, 2007 -26- Version 1.4 ...
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... R/W 00h Reserved R/W E2h R/W 21h R/W 00h R/W 00h -27- W83627DHG DESCRIPTION Software Reset Logical Device Chip ID, MSB Chip ID, LSB Device Power Down Immediate Power Down Global Option Interface Tri-state Enable Global Option Global Option Multi-function Pin Selection SPI Configuration ...
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... The W83627DHG provides hardware access to all monitored parameters through the LPC or I interface and software access through application software, such as Winbond’s Hardware Doctor BIOS. In addition, the W83627DHG can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. ...
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... BANK 0 BANK 0 BANK 0 Smart Fan Configuration Smart Fan Configuration Smart Fan Configuration Registers Registers Registers 60h~6Ah 60h~6Ah 60h~6Ah Publication Release Date: Aug, 22, 2007 -29- W83627DHG BANK 0 BANK 0 BANK 0 FANOUT Critical FANOUT Critical FANOUT Critical Temperature Temperature Temperature 6Bh~6Eh 6Bh~6Eh 6Bh~6Eh BANK 1 BANK 1 ...
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... I C interface 2 This interface uses the I C Serial Bus to access the internal registers. The W83627DHG has a programmable serial-bus address that is controlled by index 48h. The two timing diagrams below illustrate how to use the I how to read the value in an internal register, respectively. (a) Serial bus write to internal address register followed by the data byte ...
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... CAP,2200p CPUD-(AGND) Pin 105 CPUD- (AGND) (+12 V) should be reduced before it is connected × 2 VIN -31- W83627DHG Pin 95 Pin 74 Pin 61 Pin 12 Pin 100 Pin 99 Pin 97 8-bit ADC Pin 96 with 8mV LSB Pin 98 R4 Pin 101 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... The W83627DHG uses the same approach. Pins 12 and 95 provide two functions. One, these pins are connected to VCC at +3 supply internal (digital / analog) power to the W83627DHG. Two, these pins monitor VCC. The W83627DHG has two internal, 34-KΩ serial resistors that reduce the ADC-input voltage to 1 ...
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... Monitor Temperature from Thermal Diode (Voltage Mode) The thermal diode D- pin is connected to CPUD-(pin 105), and the D+ pin is connected to the temperature sensor pin in the W83627DHG. A 15-KΩ resistor is connected to VREF to supply the bias current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise. ...
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... Monitor Temperature from Thermal Diode (Current Mode) The W83627DHG can also sense the diode temperature through Current Mode and the circuit is shown in the following figure. The pin of processor D- is connected to CPUD-(pin 105) and the pin D+ is connected to temperature sensor pin in the W83627DHG. A bypass capacitor C=2200pF should be added to filter the high frequency noise ...
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... Voltage Data Format The W83627DHG can return five (5) voltage values through the SST interface. The voltage data format is 16-bit two’s-complement binary. The relation between the 2-byte data and the monitored voltage is listed below: 1) CPUVCORE (pin 100) = Decimal[2-byte data by GetVoltVccp 1024 volts 2) 3VCC (pin 12) = Decimal[2-byte data by GetVolt3p3V()] / 1024 volts 3) “ ...
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... Program Logical Device C, CR[E0h] bit (7..4) for each PECI Agent. Setting to “1” enables the W83627DHG to access the agent. The power-on default is disabled. After an agent is enabled, the W83627DHG issues PING and GetTemp commands to obtain the PECI temperature ...
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... Please be noted that when the temperature source is selected as PECI, the CPUTIN or AUXTIN register reading does not reflect the actual temperature of processor addition, the W83627DHG provides a PECISB pin that can be connected to a PECI host (e.g. chipset), so the W83627DHG becomes a bridge between that PECI host and the PECI client (e.g. CPU with PECI function) ...
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... A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI Agent to report whether the W83627DHG (PECI host) detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successive times. ...
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... Fan Speed Measurement The W83627DHG can measure fan speed for fans equipped with tachometer outputs. The tachometer signals should be set to TTL-level, and the maximum input voltage cannot exceed +3 the tachometer signal exceeds +3 external trimming circuit should be added to reduce the voltage accordingly ...
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... Fan Speed Control The W83627DHG has four output pins for fan control, each of which offers PWM duty cycle and DC voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0 Index 04h, bits Index 12h, bit 0; and Index 62h, bit 6. ...
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... TM 7.6 Control MART AN The W83627DHG supports two S TM Cruise mode—and S F MART TM enabling features, fan output starts from the previous setting in Bank0 Index 01h, Index MART AN 03h, Index 11h and Index 61h There are four pairs of temperature sensors and fan outputs in S figure below ...
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... The following figures illustrate two examples of Thermal Cruise W83627DHG TM mode. Publication Release Date: Aug, 22, 2007 -42- TM ...
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... If the fan speed count is lower than the low end (e.g., 150), fan output decreases to make the count higher. One example is illustrated in this figure. Mode -43- W83627DHG TM mode. Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... AUXTIN Temperature Sensor CPUFANOUT0 Output Value Select SYSFANOUT Output Value Select AUXFANOUT Output Value Select CPUFANOUT1 Output Value Select -44- W83627DHG ATTRIBUTE BIT DATA 8 MSB, 1°C bit 7, Read only 0.5 °C Read only 8 MSB, 1°C 8 MSB, 1°C bit 7, Read only 0.5 °C ...
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... Bank0, Index 07h, 12h, Bit4 bits 4-7 Bank0, Index Bank0, Index 14h, 12h, Bit3 bits 0-3 Bank0, Index Bank0, Index 62h, 12h, Bit6 bits 0-3 -45- W83627DHG KEEP MIN. STEP- FAN STOP STEP-UP DOWN OUTPUT TIME TIME TIME VALUE Bank0, 12h, Bank0, Bit5 ...
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... The target temperature, temperature tolerance, maximum and minimum fan outputs and step are set. (2) The following figure shows the initial conditions. If the current temperature is within (Target Temperature ± Temperature Tolerance), the fan speed remains constant. W83627DHG Pin 115 CPUFANOUT0 Pin 120 ...
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... Tar 3 Tar 3 Tar Tar Tar Tar Tar 2 Tar 2 Tar 2 Tar 2 Tar 5 Tar 5 Tar 5 Tar 5 Tar 4 Tar 4 Tar 4 Tar 4 -47- W83627DHG Temperature Temperature Tol. Tol. Tol. Tol. Step Step Step Step Temperature Temperature Temperature Temperature Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Bank0 Index 12h, bit 4 and bit 6, and the stop value is specified in Bank0 Index 09h and Index 64h. The fan remains at the stop value for the period of time defined in Bank0 Index 0Dh and Index 66h. Tolerance Tolerance Tar Tar Tar 2 Tar 2 Tar 3 Tar 3 Tar 1 Tar 1 -48- W83627DHG Temperature Temperature Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Bank0, Index Bank0, 62h, bits 0-3 Index 64h STEP DOWN STEP UP TIME TIME Bank0, Index Bank0, 0Eh Index 0Fh -49- W83627DHG BIT DATA 8 MSB, 1°C bit 7, 0.5 °C 8 MSB, 1°C 8 MSB, 1°C bit 7, 0.5 °C bits 7~0 CPUFANOUT0 Value bits 7~0 CPUFANOUT1 Value MAX ...
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... If the interrupt is reset, the SMI# pin continues to create interrupts until the temperature goes below T Fan Count limit SMI (Temperature Hysteresis) to 127°C. HYST . This is illustrated in the figure below. O Publication Release Date: Aug, 22, 2007 -50- W83627DHG * * O Version 1.4 ...
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... HYST . Once the temperature rises above T HYST , until the temperature falls below T O (Temperature Hysteresis) lower than T HYST , however, and generates an interrupt, this mode does not O -51- W83627DHG * * Two-Time Interrupt and setting Bank0 O , however This interrupt must be reset HYST and setting Bank0 ...
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... OI T HYST SMI Comparator Interrupt Mode * *Interrupt Reset when Interrupt Status Registers are read One-Time Interrupt Mode HYST SMI *Interrupt Reset when Interrupt Status Registers are read Interrupt Mode -52- W83627DHG * O . This HYST * * Two-Time Publication Release Date: Aug, 22, 2007 Version 1.4 (Over * ...
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... *Interrupt Reset when Temperature sensor registers are read and has not yet fallen below until the temperature falls below T O Publication Release Date: Aug, 22, 2007 -53- W83627DHG O , however This interrupt must be HYST * . The HYST . HYST . Once the temperature rises HYST ...
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... Bank 0, Index 46h, bit 7, or CR[E6h] bit 5 at Logical Device A is set to “1” first and then to “0”. CASEOPEN# CASEOPEN# CASEOPEN CASEOPEN CLEAR CLEAR CASEOPEN CASEOPEN STATUS STATUS Figure 7.1 Caseopen Logic Publication Release Date: Aug, 22, 2007 -54- W83627DHG Version 1.4 ...
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... BEEP Alarm Function The W83627DHG provides an alarm output function at the BEEP/SO pin. The BEEP/SO pin is a multi-function pin and can be configured as BEEP output, if Configuration Register CR[24h], bit 1 is set to zero. The BEEP outputs a warning tone when one of the monitored parameters in the following events is out of the preset range ...
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... Power on Default Value 00h Attribute: Read/Write Size: 8 bits Bit 7-0: Data to be read from written to Value RAM and Register BIT 5 BIT 4 BIT 3 Address Pointer (Power On default 00h -56- W83627DHG Data Reserved BIT 2 BIT 1 BIT Data Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... The maximum value of the divider is 127 (7Fh), and it should not be set to 0. 8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0) Register Location: 01h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits PWM_SCALE1 PWM_CLK_SEL1 Input Clock = Pre_Scale Divider SYSFANOUT Value -57- W83627DHG 1 ∗ 256 Publication Release Date: Aug, 22, 2007 Version 1.4 i.e., ...
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... PWM output frequency. PWM output frequency = The maximum value of the divider is 127 (7Fh), and it should not be set to 0. OUTPUT Voltage = PWM_CLK_SEL2 Input Clock Pre_Scale Divider -58- W83627DHG FANOUT AVCC * 64 PWM_SCALE2 1 ∗ 256 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Bit 1-0: Reserved. 8.7 FAN Configuration Register I - Index 04h (Bank 0) Register Location: 04h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits CPUFANOUT0 Value FANOUT AVCC * SYSFANOUT_SEL CPUFANOUT0_SEL SYSFANOUT_Mode SYSFANOUT_Mode CPUFANOUT0_Mode CPUFANOUT0_Mode Reserved Reserved -59- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Thermal Cruise mode, Bit 7: Reserved. Bit 6-0: SYSTIN Target Temperature. TM (2)In Fan Speed Cruise mode, Bit 7-0: SYSFANIN Target Speed. TM Mode. TM Mode III Mode. MART AN TM Mode. TM Mode Target Temperature / Target Speed -60- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Bit 7-4: Tolerance of CPUFANIN0 Target Speed Target Temperature / Target Speed TM F III mode, MART SYSTIN Target Temperature Tolerance / SYSFANIN Target Speed Tolerance CPUTIN Target Temperature Tolerance / CPUFANIN0 Target Speed Tolerance TM F III mode, MART AN -61- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Stop Value SYSFANOUT Stop Value CPUFANOUT0 Stop Value TM F III mode, the CPUFANOUT0 value decreases to this MART AN -62- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Power on Default Value: 01h Attribute: Read/Write Size: 8 bits Thermal Cruise mode, CPUFANOUT0 value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan SYSFANOUT Start-up Value CPUFANOUT0 Start-up Value -63- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... The units are intervals of 0.1 seconds. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 seconds. The default time is 24 seconds SYSFANOUT Stop Time CPUFANOUT0 Stop Time TM F III mode, this register determines the amount of time it MART AN -64- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... The units are intervals of 0.1 second. The default time is 1 second. (2)For DC output: The units are intervals of 0.4 second. The default time is 4 seconds FANOUT Value Step Down Time FANOUT Value Step Up Time -65- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... The maximum value of the divider is 127 (7Fh), and it should not be set to 0. 8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0) Register Location: 11h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits PWM_CLK_SEL3 Input Pre_Scale AUXFANOUT Value -66- W83627DHG PWM_SCALE3 Clock 1 ∗ Divider 256 Publication Release Date: Aug, 22, 2007 Version 1.4 (i.e., ...
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... AUXFANOUT value decreases to zero when the temperature goes below the target range. 1: AUXFANOUT value decreases to the value specified in Index 17h when the temperature goes below the target range. FANOUT AVCC * AUXFANOUT_SEL AUXFANOUT_Mode AUXFANOUT_Mode AUXFANOUT_MIN_Value CPUFANOUT0_MIN_Value SYSFANOUT_MIN_Value CPUFANOUT1_MIN_Value Reserved -67- W83627DHG 64 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Power on Default Value: 00h Attribute: Read/Write Size: 8 bits (1)In Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: AUXTIN Target Temperature. TM (2)In Fan Speed Cruise mode: Bit 7-0: AUXFANIN0 Target Speed. TM Mode. TM Mode Target Temperature / Target Speed Publication Release Date: Aug, 22, 2007 -68- W83627DHG Version 1.4 ...
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... Please note that Stop Value does not mean that the fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved AUXFANOUT Stop Value -69- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... For PWM output, The units are intervals of 0.1 second. The default time is 6 seconds. (2) For DC output, The units are intervals of 0.4 second. The default time is 24 seconds AUXFANOUT Start-up Value AUXFANOUT Stop Time -70- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 83
... Note: This location stores the number of counts of the internal clock per revolution. CPUFANIN0 reading 29h Note: This location stores the number of counts of the internal clock per revolution Reserved Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved DESCRIPTION Publication Release Date: Aug, 22, 2007 -71- W83627DHG Version 1.4 ...
Page 84
... CPUFANIN1 Fan Count Limit 3Eh Note the number of counts of the internal clock for the Limit of the fan speed. CPUFANIN1 reading 3Fh Note: This location stores the number of counts of the internal clock per revolution. W83627DHG DESCRIPTION Publication Release Date: Aug, 22, 2007 -72- Version 1.4 ...
Page 85
... Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded. Bit 5: A one indicates the high limit of CPUTIN temperature has been exceeded START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION CPUVCORE VIN0 AVCC(Pin95) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0 -73- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 86
... Bit 1: A one indicates the high or low limit of VIN3 has been exceeded. Bit 0: A one indicates the high or low limit of VIN1 has been exceeded VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2 TM mode. TM mode. -74- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 87
... SMI# Mask Register 3 - Index 46h (Bank 0) Register Location: 46h Power on Default Value: 07h Attribute: Read/Write Size: 8 bits CPUVCORE VIN0 AVCC(Pin95) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0 VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2 -75- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 88
... Pin58(AUXFANIN1) generates a logic-high signal. 0: Pin58 generates a logic-low signal. (Default) Bit 0: AUXFANIN1 Input Control Reserved CPUFANIN1 AUXFANIN1 Reserved Reserved Reserved Reserved CaseOpen Clear FANINC5 FANOPV5 FANINC4 FANOPV4 SYSFANIN DIV_B0 SYSFANIN DIV_B1 CPUFANIN0 DIV_B0 CPUFANIN0 DIV_B1 -76- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 89
... Select PECI Agent 2 as AUXFANOUT monitor source. 100: Select PECI Agent 3 as AUXFANOUT monitor source Serial Bus Addr. Reserved CPUFANOUT0 TEMP_SEL[0] CPUFANOUT0 TEMP_SEL[1] CPUFANOUT0 TEMP_SEL[2] Reserved AUXFANOUT TEMP_SEL[0] AUXFANOUT TEMP_SEL[1] AUXFANOUT TEMP_SEL[2] Reserved -77- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 90
... Select PECI Agent 2 as CPUFANOUT1 monitor source. 110: Select PECI Agent 3 as CPUFANOUT1 monitor source. 111: Select PECI Agent 4 as CPUFANOUT1 monitor source. Bit 4-0: Reserved Reserved Reserved Reserved Reserved Reserved CPUFANOUT1 TEMP_SEL[0] CPUFANOUT1 TEMP_SEL[1] CPUFANOUT1 TEMP_SEL[2] -78- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 91
... Bit 7: CPUFANIN1 Divisor bit2. Bit 6: 1: SMI# output type of Temperature CPUTIN / AUXTIN is in Comparator Interrupt mode Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL AUXFANIN0 DIV_B0 AUXFANIN0 DIV_B1 Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 EN_T1_ONE T2T3_INTMode CPUFANIN1 DIV_B2 -79- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 92
... Pin112 generates a logic-low signal. (Default) Bit 2: CPUFANIN0 Input Control. 1: Pin112 (CPUFANIN0) acts as a FAN tachometer input. (Default) 0: Pin112 acts as a FAN control signal, and the output value is set by bit FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved Publication Release Date: Aug, 22, 2007 -80- W83627DHG Version 1.4 ...
Page 93
... For example, “010” selects bank2. 8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0) Register Location: Power on Default Value: Attribute: Size: 4Eh 80h Read/Write 8 bits BANKSEL0 BANKSEL1 BANKSEL2 Reserved EN_CPUFANIN1_BP EN_AUXFANIN1_BP Reserved HBACS 4Fh <15:0> = 5CA3h Read Only 16 bits -81- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 94
... Bit 3: BEEP output control for 3VCC if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 2: BEEP output control for AVCC if the monitored value exceeds the threshold value EN_CPUVCORE_BP EN_VIN0_BP EN_AVCC_BP EN_3VCC_BP EN_SYSTIN_BP EN_CPUTIN_BP EN_SYSFANIN_BP EN_CPUFANIN0_BP -82- W83627DHG VIDH VIDL Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 95
... Bit 2: BEEP output control for VIN3 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 1: BEEP output control for VIN2 if the monitored value exceeds the threshold value. 1: Enable BEEP output EN_VIN1_BP EN_VIN2_BP EN_VIN3_B P E N_AUXFANIN0_BP EN_CASEOPEN_BP EN_AUXTIN_BP EN_VIN4_BP EN_GBP Publication Release Date: Aug, 22, 2007 -83- W83627DHG Version 1.4 ...
Page 96
... CPU-compatible thermal diode. 0: Reserved. Bit 5: Diode mode selection for temperature CPUTIN, if Index 5Dh, bit2 is set CPU-compatible thermal diode. 0: Reserved CHIPID CPUFANIN1 DIV_B0 CPUFANIN1 DIV_B1 AUXFANIN1 DIV_B0 AUXFANIN1 DIV_B1 SELPIIV1 SELPIIV2 SELPIIV3 AUXFANIN1 DIV_B2 -84- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 97
... Diode sensor. 0: Thermistor sensor. Bit 1: Sensor type selection for SYSTIN. 1: Diode sensor. 0: Thermistor sensor EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved SYSFANIN DIV_B2 CPUFANIN0 DIV_B2 AUXFANIN0 DIV_B2 FAN DIVISOR BIT 2 BIT Publication Release Date: Aug, 22, 2007 -85- W83627DHG BIT 0 FAN DIVISOR 128 Version 1.4 ...
Page 98
... Temperature sensing of SYSTIN depends on the setting of Index 5Dh and 59h. (Default) Bit 0: Reserved Reserved EN_SYSTIN Current Mode EN_CPUTIN Current Mode EN_AUXTIN Current Mode EN_SYSFANOUT Critical TEMP EN_CPUFANOUT Critical TEMP EN_AUXFANOUT Critical TEMP EN_CPUFANOUT1 Critical TEMP -86- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 99
... The maximum value of the divider is 127 (7Fh), and it should not be set to 0. 8.56 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) Register Location: 61h Power on Default Value: Strap by FAN_SET2(Pin 83) Attribute: Read/Write Size: 8 bits PWM_CLK_SEL4 Input Clock Pre_Scale Divider CPUFANOUT1 Value -87- W83627DHG PWM_SCALE4 1 ∗ 256 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 100
... Bit3-0: Tolerance of select temperature source Target Temperature. TM (2)In Fan Speed Cruise mode: Bit3-0: Tolerance of CPUFANIN1 Target Speed. FANOUT AVCC * Target Temperature Tolerance / CPUFANIN1 Target Speed Tolerance CPUFANOUT1_Mode CPUFANOUT1_Mode CPUFANOUT1_SEL Reserved TM Mode. TM Mode. TM III Mode. TM III mode: -88- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 101
... Please note that Stop Value does not mean that the fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value Target Temperature / Target Speed TM F III mode: MART CPUFANOUT1 Stop Value -89- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 102
... The units are intervals of 0.1 second. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 second. The default time is 24 seconds CPUFANOUT1 Start-up Value CPUFANOUT1 Stop Time TM F III mode, if the stop value is enabled, this register MART AN -90- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 103
... CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0) Register Location: 68h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits III mode, the CPUFANOUT0 value decreases or increases by this eight-bit value, MART AN when needed CPUFANOUT0 Max. Value -91- W83627DHG CPUFANOUT0 Step Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 104
... CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0) Register Location: 6Ah Power on Default Value: 01h Attribute: Read/Write Size: 8 bits III mode, the CPUFANOUT1 value decreases or increases by this eight-bit value, MART AN when needed CPUFANOUT1 Max. Value CPUFANOUT1 Step -92- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 105
... CPUFANOUT0 will work at full speed. 8.68 AUXFANOUT Critical Temperature Register - Index 6Dh (Bank 0) Register Location: 6Dh Power on Default Value: FFh Attribute: Read/Write Size: 8 bits SYSFANOUT Threshold temperature CPUFANOUT0 Critical temperature Publication Release Date: Aug, 22, 2007 -93- W83627DHG 0 Version 1.4 ...
Page 106
... CPUFANOUT1 will work at full speed. 8.70 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: 50h Attribute: Read Only Size: 8 bits AUXFANOUT Critical temperature CPUFANOUT1 Critical temperature Publication Release Date: Aug, 22, 2007 -94- W83627DHG 0 Version 1.4 ...
Page 107
... Bit 7-5: Reserved. This bit should be set to zero. Bit 4-3: Number of faults to detect before setting OVT# output. This avoids false tripping due to noise TEMP<0> STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved -95- W83627DHG TEMP<8:1> ° C. Reserved ° C. Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 108
... Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 Bit 7: Hysteresis temperature bit 0. The nine-bit value is in units of 0.5 Bit 6-0: Reserved THYST<0> -96- W83627DHG THYST<8:1> ° C, and the default is 75 Reserved ° C. Publication Release Date: Aug, 22, 2007 Version 1.4 ° C. ...
Page 109
... Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 Bit 7: Over-temperature bit 0. The nine-bit value is in units of 0.5 Bit 6-0: Reserved TOVF<8:1> Reserved TOVF<0> ° C. Publication Release Date: Aug, 22, 2007 -97- W83627DHG ° ° C, and the default Version 1.4 ...
Page 110
... Bit 7: Temperature <0> of the AUXTIN sensor. The nine-bit value is in units of 0.5 Bit 6-0: Reserved. 8.79 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) Register Location: 52h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits TEMP<0> -98- W83627DHG TEMP<8:1> ° C. Reserved ° C. Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 111
... AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits -99- W83627DHG STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved THYST<8:1> ° C, and the default is 75 Publication Release Date: Aug, 22, 2007 Version 1.4 ° C. ...
Page 112
... Bit 7-0: Over-temperature, bits 8-1. The nine-bit value is in units of 0.5 8.83 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits THYST<0> -100- W83627DHG Reserved ° C. TOVF<8:1> ° ° C, and the default Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 113
... Bit 1: A one indicates the high or low limit of VBAT has been exceeded. Bit 0: A one indicates the high or low limit of 3VSB has been exceeded 3VSB VBAT TAR3 Reserved CPUFANIN1 AUXFANIN1 Reserved Reserved TM mode. -101- W83627DHG Reserved TOVF<0> ° C. Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 114
... Bit 7-6: Reserved. Bit 5: User-defined BEEP output function. 0: Make BEEP inactive. (Default) 1: Make BEEP active. Bit 4-2: Reserved 3VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved EN_3VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Publication Release Date: Aug, 22, 2007 -102- W83627DHG Version 1.4 ...
Page 115
... Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the read value is the sum of the monitored value and this offset value OFFSET<7:0> OFFSET<7:0> -103- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 116
... Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 5: CPUTIN temperature sensor status. 1: Temperature exceeds the over-temperature value. 0: Temperature is under the hysteresis value CPUVCORE_STS VIN0_STS AVCC_STS 3VCC_STS SYSTIN_STS CPUTIN_STS SYSFANIN_STS CPUFANIN0_STS -104- W83627DHG OFFSET<7:0> Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 117
... SYSTIN temperature has not reached the warning range. Bit 5: AUXTIN temperature sensor status. 1: Temperature exceeds the over-temperature value. 0: Temperature is under the hysteresis value VIN1_STS TAR4_STS CPUFANIN1_STS AUXFANIN0_STS CASEOPEN_STS AUXTIN_STS TAR1_STS TAR2_STS Publication Release Date: Aug, 22, 2007 -105- W83627DHG Version 1.4 ...
Page 118
... VIN2 voltage is in the allowed range. Bit 4: VIN3 Voltage status. 1: VIN3 voltage is over or under the allowed range. 0: VIN3 voltage is in the allowed range. Bit 3: Reserved VSB_STS VBAT_STS TAR3_STS Reserved VIN3_STS VIN2_STS Reserved AUXFANIN1_STS -106- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 119
... Reserved 5Ah Reserved 5Bh Reserved AUXFANIN1 Fan Count Limit 5Ch Note the number of counts of the internal clock for the Low Limit of the fan speed. 8.97 Reserved Register - Index 50h ~ 57h (Bank 6) W83627DHG DESCRIPTION Publication Release Date: Aug, 22, 2007 -107- Version 1.4 ...
Page 120
... The data are placed to the LPC bus by the Super I/O (W83627DHG) and returned to the South Bridge. All of the data are read in this manner. By setting the registers shown at Table 9.3, the Super I/O (W83627DHG) supports all the instructions given, such as erase, read, program, to SPI flash ...
Page 121
... Mode execution. Please see the Table 9.3 for the MODE details of each mode. ADD2 ADD1 ADD0 DATA0 DATA1 DATA2 DATA3 -109- W83627DHG DESCRIPTION Address [19:16] Address [15:8] Address [7:0] Data byte 0 Data byte 1 Data byte 2 Data byte 3 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 122
... First, write the “Byte Program” instruction to Base+0. Then write the addresses into Base+2 ~ Base+3 and parameters to Base+4. Last, write 5X to Base+1. For correct programming, make sure the state of the device is ready and write enabled. * For more details, please see the Programming Guide of the W83627DHG. Table 9.3 MODE FUNCTION ...
Page 123
... FLOPPY DISK CONTROLLER 10.1 FDC Functional Description The floppy disk controller (FDC) of the W83627DHG integrates all of the logic required for floppy disk control. The FDC implements a FIFO which provides better system performance in multi-master systems, and the digital data separator supports data rates bits/sec. ...
Page 124
... FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk. 10.1.5 FDC Core The W83627DHG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the microprocessor ...
Page 125
... R/W: Read/Write SC: Sectors per Cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE W83627DHG Publication Release Date: Aug, 22, 2007 -113- Version 1.4 ...
Page 126
... ST1 ----------------------- R -------------------- ST2 ----------------------- ---------------------- C ------------------------ R R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ -114- W83627DHG D2 REMARKS 0 Command codes 0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 127
... ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ DS1 DS0 -115- W83627DHG D2 REMARKS 1 Command codes 0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 128
... DS0 -116- W83627DHG D2 REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after command execution Publication Release Date: Aug, 22, 2007 ...
Page 129
... DS1 DS0 MFM DS1 DS0 -117- W83627DHG REMARKS D2 Command codes 0 The first correct ID information on the cylinder is stored in the Data Register Status information after command execution Disk status after the command has been completed REMARKS D2 1 Command codes 0 Sector ID information prior ...
Page 130
... MFM -118- W83627DHG D2 REMARKS 0 Command code 0 Enhanced controller D2 REMARKS Command codes 0 Sector ID information prior to Command execution Data transfer between the FDD and the system Status information after Command execution Sector ID information after Command execution Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 131
... ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ -119- W83627DHG D2 REMARKS Command codes 0 Sector ID information prior to command execution Data transfer between the FDD and the system Status information after command execution Sector ID information after command execution Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 132
... DS1 Execution MFM DS0 -120- W83627DHG D2 REMARKS Command codes 0 Bytes per Sector Sectors per Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D2 REMARKS 0 Command codes Head retracted to Track 0 Interrupt Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 133
... EIS EFIFO POLL | ------ FIFOTHR ----| -121- W83627DHG D2 REMARKS 1 Command code Status information at the end of each seek operation D2 REMARKS 0 Command codes D2 REMARKS 1 Command codes 0 Head positioned over proper cylinder on the diskette D2 REMARKS 0 Configure information 0 Internal registers written Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 134
... Perpendicular Mode PHASE R/W D7 Command GAP WG (18) Lock PHASE R/W D7 Command W LOCK 1 Result DIR LOCK -122- W83627DHG D2 REMARKS 1 Command codes 0 D2 REMARKS 1 Registers placed in FIFO GAP D2 REMARKS 0 Command Code D0 D2 REMARKS Command Code Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 135
... HDS Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R/W D7 Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- DS1 DS0 -123- W83627DHG D2 REMARKS 0 Command Code 0 Status information about the disk drive D2 REMARKS Invalid codes (no operation- FDC goes to standby state) ST0 = 80h Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 136
... Register Descriptions There are several status, data, and control registers in the W83627DHG. These registers are defined below, and the rest of this section provides more details about each one of them. ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 ...
Page 137
... HEAD# (Bit 3): This bit indicates the value of the HEAD# output. 0 side 1 1 side 0 INDEX (Bit 2): This bit indicates the complement of the INDEX# output DIR# WP INDEX HEAD# TRAK0 STEP F/F DRQ INIT PENDING -125- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 138
... MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows MOT EN A Reserved WE RDATA Toggle WDATA Toggle Drive SEL0 Publication Release Date: Aug, 22, 2007 -126- W83627DHG Version 1.4 ...
Page 139
... WE F/F (Bit 2): This bit indicates the complement of the latched WE# output pin. RESERVED (Bit 1) RESERVED (Bit -127- W83627DHG DSC# DSC# Reserved Reserved WE F/F WE F/F RDATA F/F RDATA F/F WD F/F WD F/F DSA# DSA# Reserved Reserved Reserved Reserved Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 140
... Motor Enable A. Motor A on when active high Reserved Reserved Reserved Tape sel 0 Tape sel Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 Publication Release Date: Aug, 22, 2007 -128- W83627DHG Version 1.4 ...
Page 141
... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. -129- W83627DHG DRIVE SELECTED None 1 2 ...
Page 142
... Mbps Default Delays 41.67 ns 83.34 ns 125.00 ns 166.67 ns 208.33 ns 250.00 ns 0.00 ns (disabled) DEFAULT PRECOMPENSATION DELAYS 125 ns 125 ns 125 ns 41.67ns 20.8 ns -130- W83627DHG 2 Mbps Tape drive Default Delays 20.8 ns 41.17 ns 62.5ns 83.3 ns 104.2 ns 125.00 ns 0.00 ns (disabled) Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 143
... The FIFO register stores data, commands, and parameters, and it provides disk-drive status information. In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627DHG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command. ...
Page 144
... CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 WP Write Protected FT Fault -132- W83627DHG RY Ready Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 145
... KB/S or 300 KB/S data rate In PS/2 Model 30 mode, the bit definitions are as follows Reserved for the hard disk controller During a read of this register, these bits are in tri-stat DSKCHG HIGH DENS# DRATE0 DRATE1 DSKCHG -133- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 146
... These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates Reserved -134- W83627DHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG# 0 DRATE0 DRATE1 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 147
... These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates Reserved -135- W83627DHG DRATE0 DRATE1 NOPREC Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 148
... Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) -136- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 149
... Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. DLS1 The following table identifies the remaining UART registers. Each one is described separately in the following sections. DLS0 Publication Release Date: Aug, 22, 2007 -137- W83627DHG DATA LENGTH 5 bits 6 bits 7 bits 8 bits Version 1.4 ...
Page 150
... Toggling Edge Toggling to Send (TDSR) (FERI) (TDCD) (CTS) Bit 1 Bit 2 Bit 3 Bit 4 Bit 1 Bit 2 Bit 3 Bit 4 Bit 9 Bit 10 Bit 11 Bit 12 Publication Release Date: Aug, 22, 2007 -138- W83627DHG Data RX Data RX Data Bit 5 Bit 6 Bit 7 TX Data TX Data TX Data Bit 5 Bit 6 Bit FIFOs ...
Page 151
... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) -139- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 152
... Loopback RI input IRQ enable Internal loopback enable CTS# toggling (TCTS) DSR# toggling (TDSR) RI falling edge (FERI) DCD# toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) -140- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 153
... Bit 0: This bit enables 16550 (FIFO) mode. This bit should be set to logical 1 before the other UFR bits are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) Publication Release Date: Aug, 22, 2007 -141- W83627DHG Version 1.4 ...
Page 154
... Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 -142- W83627DHG Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2 ...
Page 155
... PRE-DIV: 1.0 USED TO GENERATE 16X 24M HZ CLOCK 650 2304 975 1536 1430 1047 1478.5 857 1950 768 3900 384 7800 192 15600 96 23400 64 26000 58 -143- W83627DHG 16 –1). The output frequency of ERROR PERCENTAGE ** ** 0.18% 0.099 0.53% Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 156
... User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. DECIMAL DIVISOR PRE-DIV: 1.0 USED TO GENERATE 16X 24M HZ CLOCK 31200 48 46800 32 62400 24 93600 16 124800 12 249600 6 499200 3 748800 2 1497600 1 -144- W83627DHG ERROR PERCENTAGE ** ** ** ** ** ** ** ** ** Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 157
... PARALLEL PORT 12.1 Printer Interface Logic The W83627DHG parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627DHG supports the IBM XT/AT compatible parallel port (SPP), the bi-directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities Parallel Port (ECP) on the parallel port ...
Page 158
... Continued HOST CONNECTOR PIN NUMBER OF W83627DHG 12.2 Enhanced Parallel Port (EPP) The following table lists the registers used in the EPP mode and identifies the bit map of the parallel port and EPP registers. Some of the registers are used in other modes as well Notes: 1 ...
Page 159
... The CPU reads the contents of the printer control latch by reading the printer control swapper. The bit definitions are as follows: Bit 7, 6: These two bits are always read as logical 1. They can be written. Bit 5: Direction control bit TMOUT ERROR# SLCT STROBE AUTO FD INIT# SLCT IN IRQ ENABLE DIR -147- W83627DHG ACK# BUSY# Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 160
... EPP Data Port 0-3 These four registers are available only in EPP mode. The bit definitions for each data port are the same and as follows -148- W83627DHG 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 ...
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... If nWait is inactive high, the read/write cycle cannot start. It must wait until nWait changes to active low, at which time it starts as described above. W83627DHG EPP DESCRIPTION Publication Release Date: Aug, 22, 2007 -149- ...
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... Extended Capabilities Parallel (ECP) Port This port is software- and hardware-compatible with existing parallel ports, so the W83627DHG parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and reverse (peripheral-to-host) directions ...
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... Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr Publication Release Date: Aug, 22, 2007 -151- W83627DHG FUNCTION NOTE PD2 PD1 PD0 nInit autofd strobe full empty Version 1.4 ...
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... These bits are logical 0 during a read of the Printer Status Register. The bits of this status register are defined as follows Address/RLE -152- W83627DHG PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE nFault Select PError nAck nBusy Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... When the direction bit is 1, data bytes from the peripheral are read via automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO return bytes of ECP data to the system -153- W83627DHG strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are logical 1 during a read and can be written IRQx 0 IRQx 1 IRQx 2 intrValue compress IRQ RESOURCE -154- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... ECR and the write of the ECR. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally empty full service Intr dmaEn nErrIntrEn MODE MODE MODE -155- W83627DHG 1 0 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on-line. -156- W83627DHG The host relies upon Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... ECP mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. -157- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Data Compression The W83627DHG hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo. 12.3.13 FIFO Operation The FIFO threshold is set in LD0 CRO0, bit ...
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... KEYBOARD CONTROLLER The W83627DHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with - ® IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) FUNCTION BIT BIT DEFINITION 7 Reserved 6 IBM Keyboard Translate Mode 5 Disable Auxiliary Device 4 Disable Keyboard 3 Reserve System Flag 2 1 Enable Auxiliary Interrupt 0 Enable Keyboard Interrupt -160- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Auxiliary Device "Data" line is stuck low BIT BIT DEFINITION No Error Detected 00 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low 03 04 Keyboard "Data" line is stuck high -161- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... KBRESET is pulse low for 6μs (Min.) with a 14μs (Min.) delay. GATEA20 and KBRESET are controlled by either software or hardware logic, and they are mutually exclusive. Then, GATEA20 and KBRESET are merged with Port92 when the P92EN bit is set Publication Release Date: Aug, 22, 2007 -162- W83627DHG P92EN HGA20 HKBRST Version 1.4 ...
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... PLKBRST (Pull-Low KBRESET) A logical 1 on this bit causes KBRESET to drive low for 6 μS(Min.) with a 14 μS(Min.) delay. Before issuing another keyboard-reset command, the bit must be cleared Res. (1) Res. (0) Res. (0) Publication Release Date: Aug, 22, 2007 -163- W83627DHG Res. (1) SGA20 PLKBRST Version 1.4 ...
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... Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this bit is set to “0”, the W83627DHG won’t output any PME signal when any of the wake-up events has occurred and is enabled. The four registers are divided into PME status registers and PME interrupt Note ...
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... PSOUT# signal. The PSON# is directly connected to the power supply to turn on or off the power. Figure 14.2 shows the power on and off sequences. The ACPI state changes from S5 to S0, then to S5 PSON# SUSB# (Intel Chipset) SUSB# (Other Chipset) PSOUT# PSIN# 3VSB S5 State S0 State Figure 14.2 Publication Release Date: Aug, 22, 2007 -165- W83627DHG S5 State Version 1.4 ...
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... BIT [ ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627DHG adds the option of “user define mode” for the pre-defined state before AC power failure. BIOS can set the pre-defined state DEFINITION System always turns off when it returns from AC power failure ...
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... According to this setting, the system is returned to the pre-defined state after the AC power recovery. 14.2 Wake Up the System by Keyboard and Mouse The W83627DHG generates a low pulse through the PSOUT# pin to wake up the system when it detects a key code pressed or mouse button clicked. The following sections describe how the W83627DHG works. ...
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... The RSMRST# (Pin 75) signal is a reset output and is used as the 3VSB power-on reset signal for the South Bridge. When the W83627DHG detects the 3VSB voltage rises to “V1”, it then starts a delay – “t1” before the rising edge of RSMRST# asserting. If the 3VSB voltage falls below “V2”, the RSMRST# de-asserts immediately ...
Page 181
... The PWROK (Pin 71) signal is an output and is used as the 3VCC power-on reset signal. When the W83627DHG detects the 3VCC voltage rises to “V3”, it then starts a delay – “t2” before the rising edge of PWROK asserting. If the 3VCC voltage falls below “V4”, the PWROK de-asserts immediately ...
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... PWROK_DEL (VSB) Set the delay time when rising from PWROK_ST to PWROK. 00: No delay time. 10 The relation and parameter are illustrated in the Figure 14.7 -170- W83627DHG 01: Delay 32 mS 11: Delay 250 mS Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... ATXPGD signal activation is during or after t2, PWROK and PWROK2 assert or de-assert according to the 3VCC voltage and the ATXPGD signal. PARAMETER PWROK/PWROK2 are active when both 3VCC and ATXPGD are valid Figure 14.8 Publication Release Date: Aug, 22, 2007 -171- W83627DHG MIN MAX UNIT PWROK/PWROK2 ...
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... Publication Release Date: Aug, 22, 2007 -172- W83627DHG V4 PWROK/PWROK2 are inactive even when 3VCC is valid UNIT NOTE For both UBC and UBE V version For both UBC and UBE V version V For UBF version V For UBF version mS Version 1 ...
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... H=Host Control SL=Slave Control Note: 1. The Start Frame pulse can be 4-8 clocks wide. 2. The first clock of Start Frame is driven low by the W83627DHG because IRQ1 of the W83627DHG needs an interrupt request. Then the host takes over and continues to pull the SERIRQ low. IRQ0 FRAME H ...
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... IRQ/Data Frame Once the Start Frame has been initiated, the W83627DHG must start counting frames based on the rising edge of the start pulse. Each IRQ/Data Frame has three clocks: the Sample phase, the Recovery phase, and the Turn-around phase. During the Sample phase, the W83627DHG drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then SERIRQ must be left tri-stated ...
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... The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame. IRQ15 IOCHCK# FRAME FRAME None T=Turn-around -175- W83627DHG STOP FRAME NEXT CYCLE STOP START Host Controller S=Sample I= Idle. Publication Release Date: Aug, 22, 2007 Version 1.4 2 ...
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... The W83627DHG outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In other words, when the value is counted down to zero, the timer stops, and the W83627DHG sets the WDTO# status bit in Logical Device 8, CR[F7h], bit[4], outputting a low signal to the WDTO# pin(pin 77). ...
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... GENERAL PURPOSE I/O The W83627DHG provides 40 input/output ports that can be individually configured to perform a simple basic I/O function or alternative, pre-defined function. GPIO port 6 is configured through control registers in Logical Device 7, and GPIO ports Logical Device 9. Users can configure each individual port input or output port by programming respective bit in selection register (0 = output input) ...
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... VID INPUTS AND OUTPUTS The W83627DHG provides eight pins for VID input or output function. The default function is VID input. These pins can be configured to VID output function by setting Logical Device B, CR[F0h], bit The configuration is applied to the 8 pins as a group. None of them can be individually set to input or output ...
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... PCI RESET BUFFERS The W83627DHG has five copies of LRESET# output buffers. LRESET# is LPC Interface Reset, to which PCI Reset is connected. The five copies of LRESET# in the W83627DHG are designated RSTOUT0#, RSTOUT1#, RSTOUT2#, RSTOUT3# and RSTOUT4#. All of them are powered by a 3VSB power. RSTOUT0 open-drain output buffer of LRESET#. This signal needs an external pulled-up resistor of 3 ...
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... BIT READ / WRITE 7~1 Reserved. IPD (Immediate Power Down). When set to 1, the whole chip is put into power-down mode immediately. W83627DHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 0: Powered down. 1: Not powered down. 0: Powered down. 1: Not powered down. 0: Powered down. 1: Not powered down. ...
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... CPUFANOUT1 is Push-pull. (Default) CPUFANOUT1 is Open-drain. AUXFANOUT is Push-pull. (Default) AUXFANOUT is Open-drain. SYSFANOUT is Open-drain. (Default) SYSFANOUT is Push-pull. CPUFANOUT0 is Open-drain. (Default) CPUFANOUT0 is Push-pull. Enable Serial Peripheral Interface Pin 2 SCK Pin 19 SCE Pin 58 SI Pin 118 SO -181- W83627DHG s: value by strapping Publication Release Date: Aug, 22, 2007 Version 1.4 ...
Page 194
... Disable UART B legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is not effective when selecting IRQ. DESCRIPTION s: value by strapping DESCRIPTION address + 4) bit 3 is effective when selecting IRQ. address + 4) bit 3 is effective when selecting IRQ. Publication Release Date: Aug, 22, 2007 -182- W83627DHG Version 1.4 ...
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... Disable decoding of BIOS ROM range at FFE xxxxx. Parallel Port Mode. Reserved. DESCRIPTION OVT# SMI# UART A GPIO6 Bit-1 Pin 119 ~ 120 0 0 (Default Pin 119 ~ 120 -183- W83627DHG Pin 119 ~ 120 function CPUFANIN1, CPUFANOUT1 GP21, GP20 Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Normal read. SPI clock is 22MHz. Reserved. Normal read. The clock rate is based on the setting of CR[2Ah], bits[7:6] Reserved Reserved Fast read with one dummy byte. The clock rate is 33MHz interface) set by CR2C bits[6:5]. SDA, SCL. -184- W83627DHG Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Enable thermal shutdown function. Pins function select Bit 1~0 DESCRIPTION Bit-0 Pin 82 Reserved 0 0 Pin 83 Reserved Others GPIO4 Pin 82 IRRX 0 1 Pin 83 IRTX Others GPIO4 1 0 Pins Pins -185- W83627DHG Pins function ( tri-state) ( always low) GPIO4 UART B Publication Release Date: Aug, 22, 2007 Version 1.4 ...
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... Pin 77 Select (reset by RSMRST WDTO GPIO50 CR 2Eh. (Default 00h) BIT READ / WRITE 7 Test Mode Bits: Reserved for Winbond. CR 2Fh. (Default 00h) BIT READ / WRITE 7 Test Mode Bits: Reserved for Winbond. W83627DHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: Aug, 22, 2007 -186- Version 1.4 ...
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... A. (PS2 mode only) Swap Drive 0, 1 Mode => Swap. Interface Mode. 3 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. DESCRIPTION 1: Drive and Motor select 0 and 1 are swapped. 00: Model 30. 01: PS/2. 10: Reserved. 11: AT Mode Publication Release Date: Aug, 22, 2007 -187- W83627DHG 011: DMA3. Version 1.4 ...
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... Drive Type selection (Refer to TABLE B). DESCRIPTION 0: Burst Mode is enabled 1: Non-Burst Mode. 0: Normal Floppy Mode. 1: Enhanced 3-mode FDD. DESCRIPTION 00: FDD A. 01: Reserved. 10: Reserved. 11: Reserved. 01: Normal. 11: 0 (Forced to logic 0). DESCRIPTION DESCRIPTION 10: 2 Meg Tape. 11: Reserved. Publication Release Date: Aug, 22, 2007 -188- W83627DHG Version 1.4 ...