W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 161

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When any EPP data port is accessed, the contents of DB0-DB7 are buffered (non-inverting) and output
to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle
to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
12.2.6 EPP Pin Descriptions
12.2.7 EPP Operation
When EPP mode is selected, the PDx bus is in standard or bi-directional mode when no EPP read,
write, or address cycle is being executed. In this situation, all output signals are set by the SPP Control
Port and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 μs have
elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is
aborted when a time-out occurs. The time-out condition is indicated in status bit 0.
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read,
and Data Read. All operations on the EPP device are performed asynchronously.
12.2.7.1. EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If nWait is active low, the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle
(nWrite active low, nDStrb/nAStrb active low) starts, proceeds normally, and is completed when nWait
goes inactive high.
b. If nWait is inactive high, the read/write cycle cannot start. It must wait until nWait changes to active
low, at which time it starts as described above.
NWrite
PD<0:7>
Intr
NWait
PE
Select
NDStrb
Nerror
Ninits
NAStrb
EPP NAME
TYPE
I/O
O
O
O
O
I
I
I
I
I
Denotes read or write operation for address or data.
Bi-directional EPP address and data bus.
Used by peripheral device to interrupt the host.
Inactivated to acknowledge that data transfer is complete. Activated to
indicate that the device is ready for the next transfer.
Paper end; same as SPP mode.
Printer-select status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
This signal is active low. It denotes an address read or write operation.
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EPP DESCRIPTION
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4