W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 222

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR FEh. (GPIO3 Event Route Selection Register; Default 00h)
20.12
CR 30h. (Default 00h)
CR 60h, 61h. (Default 00h, 00h)
CR 70h. (Default 00h)
7~1
7~0
7~4
3~0
BIT
BIT
BIT
BIT
7
6
5
4
3
2
1
0
0
Reserved.
Reserved.
READ / WRITE
READ / WRITE
READ / WRITE
READ / WRITE
Logical Device B (Hardware Monitor)
Reserved.
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
Reserved.
0: Disable GP35 event route to PSOUT#.
1: Enable GP35 event route to PSOUT#.
0: Disable GP31 event route to PSOUT#.
1: Enable GP31 event route to PSOUT#.
0: Disable GP30 event route to PSOUT#.
1: Enable GP30 event route to PSOUT#.
0: Disable GP35 event route to PME#.
1: Enable GP35 event route to PME#.
0: Disable GP31 event route to PME#.
1: Enable GP31 event route to PME#.
0: Disable GP30 event route to PME#.
1: Enable GP30 event route to PME#.
0: Logical device is inactive.
1: Logical device is active.
These two registers select the HM base address <100h : FFEh> along a
two-byte boundary.
These bits select the IRQ resource for HM.
-210-
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4