Z16M1720ASG1868 Zilog, Z16M1720ASG1868 Datasheet - Page 272

• Manufacturer Part Number: Z16M1720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z16M1720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

252
Table 7. Bisync Receive Mode
UM008101-0601
Function
Initialize WR0
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Register Information Loaded
WR0
WR2
WR0
WR4
WR0
WR5
WR0
WR3
WR0
WR6
WR0
WR7
CRC character has been loaded to the receive buffer, or 20 times (the
previous 16 plus 3-bit buffer delay and 1-bit input delay) after the last bit
is at the RxD input, before CRC calculation is complete. A faster external
clock can be gated to the Receive Clock input to supply the required 16
cycles. The Transmit and Receive Data Path diagram (Figure 109) illus-
trates the various points of delay in the CRC path.
The typical program steps that implement a half-duplex Bisync Receive
mode are illustrated in Table 7. The complete set of command and status
bit definitions are explained under
Typical Program Steps
Channel Reset, Reset Receive CRC
Checker
Pointer 2
Interrupt Vector
Pointer 4
Parity Information, Sync Modes
Information, Clock Mode
Pointer 5, Reset External Status
Interrupt
Bisync CRC-16, Data Terminal Ready
Pointer 3
Sync Character Load Inhibit, Receive
CRC Enable; Enter Hunt Mode, Auto
Enables, Receive Character Length
Pointer 6
Sync Character 1
Pointer 7
Sync Character 2
“Programming” on page
Comments
Reset SIO; initialize receive CRC
checker
Channel B only
Issue Receive Parameters
Sync Character Load Inhibit strips all
the leading sync characters at the
beginning of the message. Auto Enables
enables the receiver to accept data only
after the DCD input is active.
Serial Input/Output
272.