Z8601720ASG Zilog, Z8601720ASG Datasheet
Z8601720ASG
Specifications of Z8601720ASG
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Z8601720ASG Summary of contents
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... Document Disclaimer © 2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ...
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BSY IREQ ...
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Image Bond-Out Options • • • • • • • • • ...
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TT ...
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Figure 1 Address Decoder PCMCIA Configuration Registers PCMCIA Interface PCMCIA Memory PC_A[25:11] and I/O (16-Bit) Attribute Memory (256 Bytes) Window Decoder Peripheral Bus Interface (16-Bit) Control EEPROM Registers Sequencer SPI Control ATA/IDE or Peripheral Bus Local Serial EEPROM m P ...
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Figure 2 1eh 1Eh 1Ch 30h FFh 1Eh 1Ch 00 CFh ...
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PCMCIA Bus PC_DATA 15:0 PC_HA 10:0 PC_RDY/BSY/IREQ/HINT PC_WAIT/IOCHRDY PC_HCE1/HCS0 PCMCIA PC_HCE2/HCS1 Host PC_ATA/HOE PC_HIOR PC_HIOW PC_HWE PC_REG/DACK PC_HRESET/HRESET PC_BVD1/STSCHG/PDIAG PC_WP/IOIS16/IOCS16 PC_BVD2/SPKR/DASP/DREQ PC_INPACK/DREQ Local Peripheral Bus ATA_DATA 15:0 Z86017 ATA_HCS0 ATA_HCS1 Attribute Memory ATA_HA0 ATA_HA1 ATA_HA2 Window 1 Start/Range Decoder ATA_HIOR ...
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Figure 3 08h Figure 26 09h m 0Ah 2Fh 09h ...
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PCMCIA Bus PC_DATA 15:0 PC_HA 10:0 PC_RDY/BSY/IREQ/HINT PC_WAIT/IOCHRDY PC_HCE1/HCS0 PCMCIA PC_HCE2/HCS1 Host PC_ATA/HOE PC_HIOR PC_HIOW PC_HWE PC_REG/DACK PC_HRESET/HRESET PC_BVD1/STSCHG/PDIAG PC_WP/IOIS16/IOCS16 PC_BVD2/SPKR/DASP/DREQ PC_INPACK/DREQ Local Peripheral Bus ATA_DATA 15:0 Z86017 ATA_HCS0 Attribute ATA_HCS1 Memory ATA_HA0 ATA_HA1 ATA_HA2 Window 1 Start/Range Decoder ATA_HIOR ...
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PCMCIA Bus PC_DATA 15:0 PC_HA 10:0 PC_RDY/BSY/IREQ/HINT PC_WAIT/IOCHRDY PC_HCE1/HCS0 PCMCIA PC_HCE2/HCS1 Host PC_ATA/HOE PC_HIOR PC_HIOW PC_HWE PC_REG/DACK PC_HRESET/HRESET PC_BVD1/STSCHG/PDIAG PC_WP/IOIS16/IOCS16 PC_BVD2/SPKR/DASP/DREQ PC_INPACK/DREQ EEPROM Programming Registers 7F0H EEPROM Address/Status 7F2H EEPROM Data 7F4H EEPROM Command EEPROM Commands A8H Read AAH Write ...
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Address Mapping Circuit Internal Bus, IB7-IB0 and Controls Window 0 Address 03, 04 ATA/IDE Map PCMCIA Address - Special Register and Control Bus Mapping Circuit for A TA/IDE Window 1 Address Additional Address Range 10, 11,12,13 Chip Register Select and ...
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EE_DI Serial Data In EE_Master Serial Bus Sequencer 1 = Master - Master 0 = Slave - Slave PCMCIA EEPROM ADDRESS Register PCMCIA EEPROM DATA Register PCMCIA EEPROM Command Register Serial to Parallel Shift Register Parallel to Serial EE_DO Serial ...
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Internal Bus IB7-IB0 Data In Attribute Memory PCMCIA Address Counter/ Latch Configuration Option Register, Internal Bus Card Configuration and Status, Bus Pin Replacement Register, Mux Socket and Copy Register, I/O Event Register PCMCIA Bus EEPROM Extension Registers, Address, Status, Command ...
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PC_HA10 76 VSS PC_HCE2/HCS1 PC_ATA/HOE 80 PC_HIOR PC_HIOW VDD PC_HA9 PC_HA8 85 PC_HWE PC_RDY/BSY/IREQ/HINT PC_HA7 VSS PC_HA6 90 PC_HA5 PC_HA4 PC_HRESET/HRESET VDD PC_WAIT/IOCHRDY 95 PC_HA3 PC_INPACK/DREQ PC_HA2 PC_REG/DACK PC_HA1 100 PC_BVD2/SPKR/DASP/DREQ 1 Pin Z86017/Z16017 ...
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PC_BVD2/SPKR/DASP/DREQ 76 PC_HA1 PC_REG/DACK PC_HA2 80 PC_INPACK/DREQ PC_HA3 PC_WAIT/IOCHRDY VDD PC_HRESET/HRESET 85 PC_HA4 PC_HA5 PC_HA6 VSS PC_HA7 PC_RDY/BSY/IREQ/HINT 90 PC_HWE PC_HA8 PC_HA9 VDD 95 PC_HIOW PC_HIOR PC_ATA/HOE PC_HCE2/HCS1 VSS 100 PC_HA10 1 Pin Z86M17 ...
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TT 99 ...
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TT 99 ...
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TT 99 ...
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P$ • ,QSXW • , QSXW • ,QSXW . 3XOO8S ,QSXW . 3XOO8S • • ,QSXW . 3XOO8S • ,QSXW . 3XOO8S ,QSXW . 3XOO8S • ...
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P$ ,QSXW 6FKPLWW7ULJJHUHG . 3XOO8S 2XWSXW 2XWSXW 7UL6WDWH 2XWSXW 7UL6WDWH ...
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P$ , ...
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P$ • • ,2 7UL6WDWH • ,2 7UL6WDWH 2XWSXW • • 2XWSXW • 2XWSXW ,2 7UL6WDWH ...
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P$ • 2XWSXW • ,QSXW . 3XOO8S • ,QSXW • ,QSXW . 3XOO8S • 2XWSXW • ,QSXW • , ...
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P$ • 2XWSXW ,2 7UL6WDWH ,2 7UL6WDWH ...
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P$ 7UL6WDWH • • , • , • ,QSXW . 3XOO8S • QSXW 6FKPLWW7ULJJHUHG . 3XOO8S ...
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P$ • ,QSXW TT • ,QSXW 99Ã ,QSXW . 3XOO8S ...
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• • • • 00h ...
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PC_HA<10:0> PC_HCE1 PC_HWE or PC_HOE PC_WAIT ATA_HA<2:0> Valid Even Address ATA_HCS<1:0> ATA_HIOR ATA_HIOW ATA_IOCHRDY Internal Clock (PC_MCLK_IN /2) Count 0 Internal Strobe Delay (HIOR/HIOW) Count 0 Internal Access Delay (HIOR/HIOW) HIOR/HIOW strobe delay equals IOCHRDY time plus strobe width period ...
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PCMCIA Host Writes PC_DATA<15-8> Data MUX PC_DATA<7-0> • • PC_DATA<15-8> ATA_DATA<7-0> PC_DATA<7-0> PCMCIA Host Reads Data Reciever Data ATA_DATA<7-0> Latch ...
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ENABLE_RDY_BSY(REG_00 [4]) +READY/–BUSY LEVEL IRQ I0 Mx2x1 PULSE_IREQ I1 S CCR0 [6] EN_CTR_IRQ,REG_00 [ PC_RDY/BSY/IREQ/HINT Mx2x1 I0 BSY IREQ ...
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PC_WP/IOIS16/IOIS16 I0 IOIS16 Mx2x1 I1 S EN_WP1 EN_WP2 EN_WP3 MEM_ACCESS ATA_PDASP/EXTP_WP EN EXTP WP, REG01 [5] IO_ACCES EN_WP1, REG12 [3] EN_WP1, REG16 [3] EN_WP1, REG1A [3] ATA_IOCS16 ...
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PC_WP/IOIS16/IOIS16 I0 Mx2x1 I1 S EN_WP1 EN_WP2 EN_WP3 MEM_ACCESS EN EXTP WP, REG01 [5] IO_ACCES EN_WP1, REG12 [3] EN_WP1, REG16 [3] EN_WP1, REG1A [3] ATA_PDASP/EXTP_WP ATA_IOCS16 ...
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PC/BVD2/SPKR/DASP/DREQ I1 Mx2x1 I0 S PCMCIA_MODE IORD CE1 CE2 PC_INPACK/DREQ I1 Mx2x1 I0 S ATA_MODE PC_BVD1/STSCHG/PDIAG I0 Mx2x1 I1 S PCMCIA_MODE PC_REG/DACK MAP1_DMACK MAP2_DMACK MAP3_DMACK PCMCIA_MODE MAPn_DMACK = EN_DMA_ACKn & MAPn_ACC EN_DASP,REG2 [3] EN_DASP_EXT,REG2 [7] EN_DASP_INT,REG2 [6] PDASP_SET,REG2 [2] I0 ...
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PC/BVD2/SPKR/DASP/DREQ SPKR/DASP/DREQ Mx2x1 S PCMCIA_MODE IORD CE1 CE2 PC_INPACK/DREQ I1 Mx2x1 I0 S PC_BVD1/STSCHG/PDIAG Mx2x1 S PC_REG/DACK MAPn DMACK = EN DMA ACKn & MAPn ACC EN_DASP,REG2 [ Mx4x1 EN_SPKR,REG02 [5] BVD_CTRL,REG26 ...
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D P TUB 7D6T 99 99 ...
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88Ã PCÃ PCÃÃ PGÃ PCÃ PGÃ ...
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All inputs driven to 0V, VCC and outputs floating. 2. EN_Pads Bit Set, PC_MCLK=0, EE_SK ...
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PC_HA <10:0> PC_REG PC_HCE1 10 PC_HOE PC_HWE PC_DATA <15:0> Note: PC_REG is active Low for Attribute Memory reads only ...
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PC_HA <10:0> PC_REG PC_HCE1 or PC_HCE2 10 PC_HOE PC_HWE PC_DATA <15:0> PC_WAIT Note: PC_REG is active Low for Attribute Memory reads only ...
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PC_HA <10:0> PC_REG PC_HCE1 or PC_HCE2 PC_HWE PC_HOE PC_DATA <15:0> Data Out PC_DATA <15:0> Note: PC_REG is active Low for Attribute Memory reads only Data In 27 ...
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PC_HA <10:0> PC_REG PC_HCE1 or PC_HCE2 PC_HWE PC_HOE PC_DATA <15:0> PC_WAIT Note: PC_REG is active Low for Attribute Memory reads only ...
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PC_HA <11:0> PC_REG PC_HCEx PC_IORD 38 PC_INPACK PC_IOIS16 46 PC_WAIT PC_DATA <15:0> (In Data ...
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PC_HA <11:0> PC_REG PC_HCEx PC_IOWR 54 PC_IOIS16 PC_WAIT 60 PC_DATA <15:0> Data Out ...
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PC_HA <10:0> ATA_HA <2:0> PC_DATA <15:0> ATA_DATA <15:0> PC_HIOW, /PC_HIOR PC_HCE1, PC_HCE2 ATA_HIOW, /ATA_HIOR ATA_HCS0, ATA_HCS1 PC_WE, /OE ATA_HIOW, ATA_HIOR ATA_MRD, ATA_MWR ...
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Output Load (pF 100 ...
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PC_MCLK_IN 76 EE_CS EE_SK Read Sync Bit CMD Address EE_DO Master Mode Read EEPROM Timing EE_DI Write Sync Bit CMD Address EE_DO Master Mode Write EEPROM Timing EE_DI EE_CS 70 EE_SK 73 ...
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EE_CS 77 EE_SK 8-Bit Address Command D7 D6D5D4D3 D2D1 D0D7 EE_DI Tri-State EE_DO Slave Read Command EE_CS EE_SK D7 D6D5D4 D3 D2D1 D0D7 EE_DI 8-Bit Address Command ...
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PC_HRESET/HRESET /POR /ATA_HRESET EE_CE PCMCIA Mode Bit 5 Register 03H = s/@ 20 MHz m 65 s/@ 20 MHz + EE accesses in Master Mode PC_HRESET/HRESET m 40 s/@ 20 MHz s/@ 20 MHz ...
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... Z 16017 Z16017, 20 MHz, VQFP, 0 Environmental Flow Temperature Package Speed Product Number Zilog Prefix • +70 • C, Plastic Standard Flow ...
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