UJA1069TW24/3V0,51 NXP Semiconductors, UJA1069TW24/3V0,51 Datasheet - Page 14

• Manufacturer Part Number: UJA1069TW24/3V0,51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V0,51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280016518; UJA1069TW24/3V0-T; UJA1069TW24/3V0-T

NXP Semiconductors
UJA1069_3
Product data sheet
6.4.3 Watchdog time-out behavior
6.4.4 Watchdog OFF behavior
Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active
watchdog operates in Time-out mode. The watchdog has to be triggered within the actual
programmed period time; see
wake-up events to the host microcontroller from Standby mode and Sleep mode.
In Standby and in Flash mode the nominal periods can be changed with any SPI access
to the Mode register.
Any illegal watchdog trigger code results in an immediate system reset, entering Start-up
mode.
In Standby mode and Sleep mode it is possible to switch off the watchdog entirely. For
fail-safe reasons this is only possible if the microcontroller has stopped program
execution. To ensure that there is no program execution, the V1 supply current is
monitored by the SBC while the watchdog is switched off.
When selecting the watchdog OFF code, the watchdog remains active until the
microcontroller supply current has dropped below the current monitoring threshold I
After the supply current has dropped below the threshold, the watchdog stops at the end
of the watchdog period. In case the supply current does not drop below the monitoring
threshold, the watchdog stays active.
If the microcontroller supply current increases above I
the watchdog is restarted with the last used watchdog period time and a watchdog restart
interrupt is forced, if enabled.
In case of a direct mode change towards Standby mode with watchdog OFF selected, the
longest possible watchdog period is used. It should be noted that in Sleep mode V1
current monitoring is not active.
Fig 6. Watchdog triggering using Time-out mode
(with different duration if
trigger
via SPI
trigger restarts period
possible
earliest
trigger
point
desired)
Rev. 03 — 10 September 2007
trigger range
Figure
period
6. The Time-out mode can be used to provide cyclic
trigger range
new period
possible
trigger
latest
point
time-out
thH(V1)
LIN fail-safe system basis chip
while the watchdog is OFF,
UJA1069
© NXP B.V. 2007. All rights reserved.
time-out
mce627
thL(V1)
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