CLC014AJE-TR13/NOPB National Semiconductor, CLC014AJE-TR13/NOPB Datasheet - Page 9

• Manufacturer Part Number: CLC014AJE-TR13/NOPB
• Description: IC CABLE EQUALIZER ADAPT 14-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC014AJE-TR13/NOPB

• Applications: Medical
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Mounting Type: Surface Mount
• For Use With: SD901EVK - BOARD EVAL CLC014, 016, 011, 006SD014EVK - BOARD EVALUATION CLC014
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Lead Free Status / Rohs Status: Compliant
• Other names: *CLC014AJE-TR13; *CLC014AJE-TR13/NOPB; CLC014AJE-TR13

DEVICE TESTING
Performance or compliancy testing of the CLC014 with Cable
Clones is not allowed. Use of these devices is contrary to the
product's specifications and test procedures. Testing for prod-
uct specifications or performance using cable clones is invalid
since cable clones have a different frequency response than
the actual cable. Testing with full length cable samples is rec-
ommended.
Input Interfacing
The CLC014 accepts either differential or single-ended input
voltage specified in Static Performance. The following sec-
tions show several suggestions for interfaces for the inputs
and outputs of the CLC014.
SINGLE-ENDED INPUT INTERFACE: 75Ω Coaxial Cable
The input is connected single-ended to either DI or DI as
shown in
the effects of noise. Use the equivalent termination of 37.5Ω
to balance the input impedance seen by each pin. It also helps
to terminate grounds at a common point. Resistors R
R
izer inputs are self-biasing. Signals should be AC coupled to
the inputs as shown in
DIFFERENTIAL INPUT INTERFACE: Twisted Pair
A recommended differential input interface is shown in
4. Proper voltage levels must be furnished to the input pins
and the proper cable terminating impedance must be provid-
ed. For Category 5 UTP this is approximately 100Ω.
4
data over a twisted pair. Resistors R
proper terminating impedance and signal level adjustment.
The blocking capacitors provide AC coupling of the attenuat-
ed signal levels. The plots in the Typical Performance Char-
acteristics section demonstrate various equalized data rates
using Category 5 UTP at 100 meter lengths. A full schematic
of a recommended driver and receiver circuit for 100Ω Cate-
gory 5 UTP is provided in the Typical Applications section
with further explanation.
shows a generalized network which may be used to receive
y
FIGURE 3. Single-Ended 75Ω Cable Input Interface
are recommended for optimum performance. The equal-
Figure
3. Balancing unused inputs helps to lessen
Figure
3.
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and R
2
provide the
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Figure
Figure
x
and
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9
Output Interfacing
The outputs DO and DO produce ECL logic levels when the
recommended output termination networks are used. The DO
and DO pins are not complementary emitter coupled log-
ic outputs. Instead, the outputs are taken off of the collectors
of the transistors. Therefore, care must be taken to meet the
interface threshold levels required by ECL families. Recom-
mended interfaces for standard ECL families are shown in the
following circuits.
DIFFERENTIAL LOAD-TERMINATED OUTPUT
INTERFACE
Figure 5
differential output that is terminated at the load. A diode or
75Ω resistor provides a voltage drop from the positive supply
(+5V for PECL or Ground for ECL operation) to establish
proper ECL levels. The resistors terminate the cable to the
characteristic impedance. The output voltage swing is deter-
mined by the CLC014 output current (10 mA) times the ter-
mination resistor. For the circuit in
output voltage swing is 750 mV.
DIFFERENTIAL SOURCE-TERMINATED OUTPUT
INTERFACE
Figure 6
provided at the source. This configuration may also be used
for single-ended applications. However, the unused output
must still be terminated as shown.
FIGURE 5. Differential Load Terminated
is similar to
shows a recommended circuit for implementing a
FIGURE 4. Twisted Pair Input Interface
Output Interface
Figure 5
except that the termination is
Figure
5, the nominal
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