HD64570F Renesas Electronics America, HD64570F Datasheet - Page 216

• Manufacturer Part Number: HD64570F
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RX disable state
The receiver is placed in RX disable state by a hardware reset, a channel reset, an RX reset, or
an RX disable command. In this state, the receiver ignores the input from the RXD line, and
does not perform a reception operation.
Flag wait state
The receiver waits for a flag pattern to compare it with the received bit string. (Successive
frames which share opening and closing flags can be received normally.) On detecting a flag
pattern, the receiver enters character wait state.
Character wait state
To detect a frame boundary, the receiver waits for a non-flag pattern while ignoring successive
flags. On detecting a non-flag pattern, the receiver enters address field check state.
Address field check state
The receiver checks the address field to determine whether or not to receive the associated
frame. When the address is identical to the present station address, the receiver enters
character reception state. When the address is not identical to the present station address, the
receiver enters flag wait state. In address field no-check mode, the receiver skips this check
and enters character reception state immediately after character wait state. On detecting a flag
within three character cycles after the address field check, the receiver assumes the received bit
to be a short frame, and enters character wait state.
Character receive state
The receiver transmits the received character to the receive buffer. On detecting a flag in
character receive state, the receiver transmits data up to and including the last character in the I
field when the CRCCC bit of MD0 is 1, or transmits the FCS when the CRCCC bit is 0 to the
receive buffer, and then enters character wait state.
Rev. 0, 07/98, page 200 of 453