M25PE40-VMW6TG Micron Technology Inc, M25PE40-VMW6TG Datasheet - Page 10

• Manufacturer Part Number: M25PE40-VMW6TG
• Manufacturer: Micron Technology Inc

Specifications of M25PE40-VMW6TG

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 15ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

SPI modes
3
10/62
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Standby mode and not transferring data:
Figure 4.
1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
Figure 4
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in
that the M25PE40 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
typical value of R is 100 kΩ, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
SPI interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
SPI Bus Master
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS2 CS1
shows an example of three devices connected to an MCU, on an SPI bus. Only one
Bus master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
C Q D
S
SPI memory
device
W
or
TSL
V
CC
Reset
V
R
SS
C Q D
S
Figure
SPI memory
device
SHCH
W
or
TSL
5, is the clock polarity when the
V
CC
Reset
requirement is met). The
p
V
R
SS
(C
p
= parasitic
C Q D
Figure
S
SPI memory
device
4) ensure
W
or
TSL
M25PE40
V
CC
Reset
AI13558b
V
V
V
SS
CC
SS