LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 16

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2-17. All LA-LatticeXP2 devices have six secondary clock regions and four secondary clocks (SC0 to
SC3) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-11. Secondary Clock Regions LatticeXP2-17
Figure 2-12. Secondary Clock Selection
4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region
Secondary Clock
Secondary Clock
Secondary Clock
SC0
24:1
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
SC1
24:1
Clock/Control
Secondary Clock Feedlines: 8 PIOs + 16 Routing
SC2
24:1
SC3
24:1
4 High Fan-out Data Signals (SC4 to SC7) per Region
Secondary Clock
Secondary Clock
Secondary Clock
2-13
I/O Bank 1
I/O Bank 4
Region 6
Region 5
Region 4
SC4
24:1
SC5
High Fan-Out Data
24:1
LA-LatticeXP2 Family Data Sheet
SC6
24:1
SC7
24:1
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
Architecture