TP3406N National Semiconductor, TP3406N Datasheet
TP3406N
Specifications of TP3406N
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TP3406N Summary of contents
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... Selection of Master and Slave mode operation is pro- grammed via the Microwire Control Interface A 2 048 MHz clock which may be synchronized to the sys- tem clock controls all transmission-related timing functions Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRE trademark of National Semiconductor Corporation C 1995 National Semiconductor Corporation ...
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Connection Diagram Pin Descriptions Name Description GND Negative power supply pin normally 0V All analog and digital signals are referred to this pin V Positive power supply input which must MCLK The 2 048 ...
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Pin Descriptions (Continued) Name Description CI MICROWIRE control channel serial data in- put CO MICROWIRE control channel serial data out- put CCLK Clock input for the MICROWIRE control channel CS Chip Select input which enables the MICRO- WIRE control channel ...
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Functional Description (Continued) FIGURE 3 Typical AMI Waveform at L FIGURE 4 Typical AMI Transmit Spectrum Measured at LO Output (With RBW FIGURE 5 Burst Mode Timing on the Line 11725 – 4 100 Hz ...
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Functional Description (Continued) BURST MODE OPERATION For full-duplex operation over a single twisted-pair burst mode timing is used with the line-card (exchange) end of the link acting as the timing Master Each burst from the Master consists of the B1 ...
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Functional Description (Continued) TABLE II Control and Status Register Functions Bit State Control Register Function 0 Master Mode C7 1 Slave Mode 0 Deactivate and Power Down C6 1 Power Up and Activate 0 Normal Through Connection C5 1 Loopback ...
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Timing Diagrams (Continued) FIGURE 7 B Channel Interface Timing Slave Mode Typical Applications FIGURE 8 Typical Application for Slave End Note 1 The TP3076 Programmable Combos also must be connected to the MICROWIRE interface Note 2 Only necessary if a ...
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Typical Applications (Continued) FIGURE 9 Typical Application for Master End Timing Diagrams (Continued) FIGURE 10 B Channel Interface Timing Details 11725 – 11725– 10 ...
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Timing Diagrams (Continued) FIGURE 11 D Channel Interface Timing (Master and Slave Modes C1 FIGURE 12 D Channel Interface Timing (Master Mode only 11725– 11725– 11725– ...
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Timing Diagrams (Continued) 10 ...
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... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications V to GND CC Voltage Voltage at any Digital Input V CC Electrical Characteristics and correlation with 100% electrical testing are assured by correlation with other production tests and or product design and characterization Typical characteristics are ...
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Timing Characteristics Unless otherwise noted All signals are referenced to GND Symbol Parameter MASTER CLOCK INPUT SPECIFICATIONS F Master Clock Frequency MCK Master Clock Tolerance Master Clock Input Jitter t Clock Pulse ...
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Timing Characteristics (Continued) Unless otherwise noted All signals are referenced to GND Symbol Parameter D CHANNEL INTERFACE (Figure 11 12) t Set Up Time D SDDC X Valid to DCLK Low t ...
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Definitions and Timing Conventions DEFINITIONS the d c input level above which input level is guaranteed to appear as a logical one This parameter measured by performing a function- al test ...
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... Hong Kong Ltd 49) 0-180-530 85 86 13th Floor Straight Block a Ocean Centre 5 Canton Rd 49) 0-180-530 85 85 Tsimshatsui Kowloon a Tel ( 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 a Tel ( 49) 0-180-534 16 80 Fax (852) 2736-9960 a National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...