SL811HST Cypress Semiconductor Corp, SL811HST Datasheet
SL811HST
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SL811HST Summary of contents
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... Motorola or Intel CPUs and many others. The SL811HS has 256-bytes of internal RAM, which is used for control registers and data buffer. The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant. Master/Slave ...
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Data Port, Microprocessor Interface The SL811HS microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interface to external processors or controllers. Programmed I/O or memory mapped I/O designs are supported through the 8-bit interface, ...
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PLL Clock Generator Either a 12-MHz or a 48-MHz external crystal can be used with [1] the SL811HS . Two pins, X1 and X2, are provided to connect a low-cost crystal circuit to the device as shown in Figure ...
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RAM accesses (see Section 5.6) and provide control and status information for USB transactions. Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS that enables additional features ...
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USB-A/USB-B Host Control Registers [Address = 00h, 08h] Table 3-3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h] Bit 7 Bit 6 Bit 5 Preamble Data Toggle Bit SyncSOF Bit Position Bit Name Function 7 Preamble If bit = ...
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USB-A/USB-B Host Base Length [Address = 02h, 0Ah] Table 3-5. USB-A / USB-B Host Base Length Definition [Address 02h, 0Ah] Bit 7 Bit 6 Bit 5 HBL7 HBL6 HBL5 The USB A/B Host Base Length register contains the maximum ...
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USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch] This register has two different functions depending read or written. When READ, this register contains the number of bytes left over (from ...
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Control Register 1 [Address = 05h] The Control Register 1 enables/disables USB transfer operation with control bits defined as follows. Table 3-11. Control Register 1 [Address 05h] Bit 7 Bit 6 Bit 5 Reserved Suspend USB Speed Bit Position ...
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Interrupt Enable Register [Address = 06h] The SL811HS provides an Interrupt Request Output, which can be activated for a number of conditions. The Interrupt Enable Register allows the user to select conditions that will result in an Interrupt being ...
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Bit Position Bit Name 6 Device Detect/Resume Device Detect/Resume Interrupt. 5 Insert/Remove 4 SOF timer 3 Reserved 2 Reserved 1 USB-B 0 USB-A 3.1.3.6 Current Data Set Register/Hardware Revision/SOF Counter LOW [Address = 0Eh] This register has two modes: a ...
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Table 3-17. SOF High Counter when READ [Address 0Fh] Bit 7 Bit 6 Bit 5 C13 C12 C11 When WRITING to this register the bits definition are defined as follows. Table 3-18. Control Register 2 when WRITTEN [Address 0Fh] Bit ...
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SL811HS Slave Mode Registers Table 3-19. SL811HS Slave/Peripheral Mode Register Summary Register Name EP 0 – Control Register 00h EP Base Address Register 01h EP Base Length Register 02h EP Packet Status Register ...
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Endpoint Control Registers 3.2.3.1 Endpoint n Control Register [Address a = (EP# * 10h (EP# * 10h)+8] Each endpoint set has a control register defined as follows: Table 3-22. Endpoint Control Register [Address EP0a/b:00h/08h, EP1a/b:10h/18h, EP2a/b:20h/28h, EP3a/b:30h/38h] ...
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Bit Position Bit Name Function 3 Sequence The Sequence bit indicates if the last packet was a DATA0 (0) or DATA1 (1). 2 Time-out This bit is not used in slave mode. 1 Error Error detected in transmission, this includes ...
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Bit Position Bit Name Function 4 J-K1 J-K1 and J-K0 force state control bits can be used to generate various USB bus conditions. Forcing K-state can be used for Peripheral device remote wake-up, Resume and other 3 J-K0 modes. These ...
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Interrupt Status Register, Address [0Dh] This Read/Write register serves as an Interrupt status register when it is read, and an Interrupt clear register when it is written. To clear an interrupt, the register must be written with the appropriate ...
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Bit Position Bit Name Function 6 SL811HS D+/D– “1” = change polarity (low-speed) Data Polarity Swap “0” change of polarity (full-speed) 5-0 Reserved NA 3.2.4.7 SOF Low Register, Address [15h] Read only Register contains the 7 low order ...
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... SL811HS and SL811HST-AC Physical Connections This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). 4.1 SL811HS Physical Connections 4.1.1 SL811HS Pin Layout *See Pin and Signal Description for Pins 2 and 3 in Host Mode nCS CM VDD2 DATA+ ...
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SL811HS USB Host/Slave Pin Description The SL811HS package is a 28-pin PLCC. The device requires 3.3 VDC. Average typical current consumption is less then 20 mA for 3.3V. Table 4-1. SL811HS Pin Assignments and Definitions Pin No. Pin Type ...
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The Diagram below illustrates a simple +3.3V voltage source. +5V (USB) GND 4.1.4 Package Markings (SL811HS) YYWW = Date code XXXX = Product code X.X = Silicon revision number Document 38-08008 Rev Ohms 2N2222 Zener +3.3 V ...
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... VDD1 Data+ Data- USBGnd Figure 4-2. SL811HST-AC USB Host/Slave Controller Pin Layout *See Pin and Signal Description for Pins 43 and 44 in Host Mode. 4.2.2 Mechanical Dimensions 48-Pin TQFP Note: 8. NC. Indicates No Connection. NC Pins should be left unconnected. Document 38-08008 Rev. *B nDACK* D7 nRD ...
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... SL811HST-AC USB Host Controller Pins Description The SL811HST-AC is packaged in a 48-pin TQFP. The device requires a 3.3VDC power source. The SL811HST-AC requires an external MHz crystal or Clock. Table 4-2. SL811HST-AC Pin Assignments and Definitions Pin No. Pin Type Pin Name VDD1 +3.3 VDC ...
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... Table 4-2. SL811HST-AC Pin Assignments and Definitions (continued) Pin No. Pin Type Pin Name 33 BIDIR BIDIR VDD +3.3 VDC nDACK 44 OUT Notes: 12. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications. 4.2.4 Package Markings (SL811HST-AC) YYWW = Date code XXXX = Product code X ...
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Electrical Specifications 5.1 Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation ...
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DC Characteristics Parameter V Input Voltage LOW IL V Input Voltage HIGH (5V Tolerant I/ Output Voltage LOW ( Output Voltage HIGH ( Output Current HIGH OH I Output Current LOW OL ...
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Bus Interface Timing Requirements 5.6.1 I/O Write Cycle twr nWR twasu A0 twdsu D0-D7 twcsu nCS I/O Write Cycle to Register or Memory Buffer Note: nCS an be held LOW for multiple Write cycles provided nWR is cycled. Parameter ...
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I/O Read Cycle twr nWR twasu A0 nRD twdsu D0-D7 nCS I/O Read Cycle from Register or Memory Buffer Parameter t Write pulse width WR t Read pulse width RD t Chip select set-up to nWR WCSU t A0 ...
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DMA Write Cycle 0 Parameter Description tdack nDACK low tdwrlo nDACK to nWR low delay tdakrq nDACK low to nDRQ high delay tdwrp nWR pulse width ...
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DMA Read Cycle 0-D 7 tdaccs 811 Parameter ...
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Clock Timing Specifications tclk CLK thigh Parameter Description t Clock Period (48 MHz) CLK t Clock HIGH Time HIGH t Clock LOW Time LOW t Clock rise Time RISE t Clock fall Time FALL Clock Duty Cycle 6.0 Package ...
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... Document 38-08008 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title: SL811HS USB Host/Slave Controllers Hardware Specification Document Number: 38-08008 Orig. of REV. ECN NO. Issue Date Change ** 110850 12/14/01 *A 112687 03/22/02 *B 381894 See ECN Document 38-08008 Rev. *B Description of Change BHA ...