PA28F400BVB120 Intel, PA28F400BVB120 Datasheet - Page 22

• Manufacturer Part Number: PA28F400BVB120
• Manufacturer: Intel

Specifications of PA28F400BVB120

• Density: 4Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

4-MBIT SmartVoltage BOOT BLOCK FAMILY
3.3.4.1
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from another block of the
memory. Once the erase sequence is started,
writing the Erase Suspend command to the CUI
requests that the WSM pause the erase sequence
at a predetermined point in the erase algorithm. The
status register will indicate if/when the erase
operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register command.
During erase suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to V
reduces active current draw.
To resume the erase operation, enable the chip by
taking CE# to V
command, which continues the erase sequence to
completion. As with the end of a standard erase
operation, the status register must be read, cleared,
and the next instruction issued in order to continue.
3.4
The boot block family architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks. The truth table, Table 9, clearly defines the
write protection methods.
3.4.1
For complete write protection of all blocks in the
flash device, the V
held low. When V
erase operation will result in a error in the status
register.
22
Boot Block Locking
V
PROTECTION
PP
Suspending and Resuming Erase
= V
IL
PP
, then issuing the Erase Resume
IL
PP
is below V
FOR COMPLETE
programming voltage can be
PPLK
, any program or
SEE NEW DESIGN RECOMMENDATIONS
IH
, which
3.4.2
When WP# = V
program or erase operation to the boot block will
result in an error in the status register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
when RP# = V
3.4.3
Two methods can be used to unlock the boot block:
1. WP# = V
2. RP# = V
If both or either of these two conditions are met, the
boot
programmed or erased.
3.4.4
If upgradability to 8 Mbit is required, note that the
8 Mbit in the 44-PSOP does not have a WP#
because no pins were available for the 8-Mbit
upgrade address. Thus, in this density-package
combination only, V
unlock the boot block. Unlocking with a logic-level
signal is not possible. If this functionality is
required, and 12 V is not available, consider using
the 48-TSOP package, which has a WP# pin and
can be unlocked with a logic-level signal. All other
density-package combinations have WP# pins.
V
V
V
V
V
V
PPLK
PPLK
PPLK
PPLK
PP
IL
Table 9. Write Protection Truth Table
block
WP# = V
LOCKING
RP# = V
BLOCK UNLOCKING
UPGRADE NOTE FOR 8-MBIT
44-PSOP PACKAGE
RP#
V
V
V
HH
V
IH
X
HH
IH
IH
IL
HH
will
IL
.
, the boot block is locked and any
WP#
HH
HH
IL
be
V
V
X
X
X
IH
IL
FOR BOOT BLOCK
OR WP# = V
(12 V) on RP# is required to
unlocked
All Blocks Locked
All Blocks Locked
(Reset)
All Blocks Unlocked
Boot Block Locked
All Blocks Unlocked
Write Protection
Provided
IH
and
FOR BOOT
can
be