TE28F800B5T90 Intel, TE28F800B5T90 Datasheet - Page 7

• Manufacturer Part Number: TE28F800B5T90
• Manufacturer: Intel

Specifications of TE28F800B5T90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

A
A
DQ
DQ
CE#
OE#
WE#
RP#
0
9
Symbol
–A
PRELIMINARY
0
8
–DQ
–DQ
18
7
15
OUTPUT
OUTPUT
INPUT/
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
ADDRESS INPUT: When A
this mode, A
is at a logic low, only the lower byte of the signatures are read. DQ
don’t care in the signature mode when BYTE# is low.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, intelligent identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ
Not applicable to 28F004B5.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WRITE ENABLE: Controls writes to the command register and array blocks. WE#
is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RESET/DEEP POWER-DOWN: Uses three voltage levels (V
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at V
erased. This overrides any control from the WP# input.
28F200: A[0–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]
15
/A
0
–1
Table 2. Pin Descriptions
decodes between the manufacturer and device IDs. When BYTE#
becomes the lowest order address for data output on DQ
HH
, the boot block is unlocked and can be programmed or
9
is at V
Name and Function
HH
the signature mode is accessed. During
28F200B5, 28F004/400B5, 28F800B5
IL
, V
IH
15
, and V
/A
–1
is a
0
–DQ
HH
) to
7
.
7