CY7C68001-56LFC Cypress Semiconductor Corp, CY7C68001-56LFC Datasheet - Page 19

• Manufacturer Part Number: CY7C68001-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68001-56LFC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

In order to avoid altering any other bits of the FIFOPINPOLAR
register (0xE609) inadvertently, the external master must do a
read (from POLAR register), modify the value to set/clear appro-
priate bits and write the modified value to FIFOPINPOLAR
register. The external master may read from the POLAR register
using the command read protocol as stated in
Protocol
to change the polarity as needed and write this modified value to
the FIFOPINPOLAR register.
9.4 REVID Register 0x05
These register bits define the silicon revision.
The upper nibble is the major revision. The lower nibble is the
minor revision. For example: if REVID = 0x11, then the silicon
revision is 1.1.
9.5 EPxCFG Register 0x06–0x09
These registers configure the large, data-handling SX2
endpoints, EP2, 4, 6, and 8.
configuration choices for these endpoints. Shaded blocks group
endpoint buffers for double-, triple-, or quad-buffering. The
endpoint direction is set independently—any shaded block can
have any direction.
.
Document #: 38-08013 Rev. *K
3. Send the actual value to write to the register Register (in this
REVID
Bit #
Bit
Name
Read/
Write
De-
fault
EPx-
CFG
Bit #
Bit
Name
Read/
Write
De-
fault
g. Command address write of address 0x3C
h. Command data write of upper nibble of the register value
i. Command data write of lower nibble of the register value
Note
11. Setting the endpoint buffering to invalid causes improper buffer allocation
case 0x1C)
(0x01)
(0x0C)
VALID
Major
on page 7. Modify the value with the appropriate bit set
R/W
R/W
X
7
1
7
Major
R/W
R/W
DIR
X
6
6
0
TYPE1 TYPE0
Major
R/W
R/W
5
X
5
1
Major
R/W
Figure 8-1.
R/W
X
4
4
0
Minor
R/W
SIZE
R/W
3
X
3
0
on page 11 shows the
STALL
Minor
R/W
R/W
X
2
2
0
Minor
BUF1
R/W
R/W
1
X
1
1
0x06, 0x08
Command
Minor
BUF0
R/W
R/W
0x05
X
0
0
0
9.5.1 Bit 7: VALID
The external master sets VALID = 1 to activate an endpoint, and
VALID = 0 to deactivate it. All SX2 endpoints default to valid. An
endpoint whose VALID bit is 0 does not respond to any USB
traffic. (Note: when setting VALID=0, use default values for all
other bits.)
9.5.2 Bit 6: DIR
0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for
EP6/8 are DIR = 1, IN.
9.5.3 Bit [5,4]: TYPE1, TYPE0
These bits define the endpoint type, as shown in
TYPE bits apply to all of the endpoint configuration registers. All
SX2 endpoints except EP0 default to BULK.
Table 9-3. Endpoint Type
9.5.4 Bit 3: SIZE
0 = 512 bytes (default), 1 = 1024 bytes.
Endpoints 4 and 8 can only be 512 bytes and is a read only bit.
The size of endpoints 2 and 6 is selectable.
9.5.5 Bit 2: STALL
Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the
external master sets this bit, any requests to the endpoint return
a STALL handshake rather than ACK or NAK. The Get
Status-Endpoint Request returns the STALL state for the
endpoint indicated in byte 4 of the request. Note that bit 7 of the
endpoint number EP (byte 4) specifies direction.
9.5.6 Bit [1,0]: BUF1, BUF0
For EP2 and EP6 the depth of endpoint buffering is selected via
BUF1:0, as shown in
internally set to double buffered and are read only bits.
Table 9-4. Endpoint Buffering
TYPE1
BUF1
0
0
1
1
0
0
1
1
TYPE0
Table
0
1
0
1
BUF0
0
1
0
1
9-4. For EP4 and EP8 the buffer is
Endpoint Type
Bulk (Default)
Isochronous
Interrupt
Invalid
Buffering
Invalid
CY7C68001
Double
Quad
Triple
Table
Page 19 of 45
[11]
9-3. The
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