CY7C1041B-15VI Cypress Semiconductor Corp, CY7C1041B-15VI Datasheet - Page 4

• Manufacturer Part Number: CY7C1041B-15VI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1041B-15VI

• Density: 4Mb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 18b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 210mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05142 Rev. *A
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
6. t
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
I
started.
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
OL
HZOE
/I
OH
, t
and 30-pF load capacitance.
HZCE
, and t
[8, 9]
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
CC
HZWE
(typical) to the First Access
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
Description
[7]
[6, 7]
[7]
[6, 7]
[6, 7]
[4]
Over the Operating Range
HZCE
[5]
is less than t
LZCE
, t
HZOE
Min.
is less than t
7C1041B-12
12
12
10
10
10
10
1
3
0
3
0
0
0
0
7
0
3
LZOE
Max.
power
12
12
12
6
6
6
6
6
6
, and t
HZWE
time has to be provided initially before a read/write operation is
HZWE
and t
Min.
7C1041B-15
15
15
12
12
12
12
1
3
0
3
0
0
0
0
8
0
3
is less than t
SD
.
Max.
15
15
LZWE
15
7
7
7
7
7
7
for any given device.
Min.
7C1041B-17
17
17
14
14
14
12
1
3
0
3
0
0
0
0
8
0
3
CY7C1041B
Max.
17
17
17
7
7
7
7
7
7
Page 4 of 11
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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