CY7C1312AV18-133BZC Cypress Semiconductor Corp, CY7C1312AV18-133BZC Datasheet
CY7C1312AV18-133BZC
Specifications of CY7C1312AV18-133BZC
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CY7C1312AV18-133BZC Summary of contents
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... Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1310AV18) or 18-bit words (CY7C1312AV18) or 36-bit words (CY7C1314AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge ...
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... Logic Block Diagram (CY7C1312AV18) D [17:0] 18 Address Register A (18: CLK K Gen. DOFF V REF WPS Control Logic BWS [1:0] Logic Block Diagram (CY7C1314AV18) D [35:0] 36 Address Register A (17: CLK K Gen. DOFF V REF WPS Control Logic BWS [3:0] Selection Guide Maximum Operating Frequency Maximum Operating Current Document #: 38-05497 Rev ...
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... Q17 R TDO TCK A Document #: 38-05497 Rev. *A PRELIMINARY CY7C1310AV18 (2M × 8) – 11 × 15 BGA NC/144M BWS WPS NC/288M K BWS VSS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1312AV18 (1M × 18) – 11 × 15 BGA NC/288M WPS BWS BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ ...
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... Read and Write operations. Internally, the device is organized arrays each for CY7C1310AV18 arrays each of 512K x 18) for CY7C1312AV18 and 512K arrays each of 256K x 36) for CY7C1314AV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for CY7C1314AV18 ...
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... K and K when in single clock mode. When the Read port is deselected, Q are automatically tri-stated. [x:0] CY7C1310AV18 − Q [7:0] CY7C1312AV18 − Q [17:0] CY7C1314AV18 − Q [35:0] Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected ...
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... Single Clock Mode The CY7C1312AV18 can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks ...
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... Depth Expansion The CY7C1312AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected ...
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... During the Data portion of a Write sequence : H L L-H – CY7C1310AV18 − only the upper nibble (D CY7C1312AV18 − only the upper byte (D L-H During the Data portion of a Write sequence : H L – CY7C1310AV18 − only the upper nibble (D CY7C1312AV18 − only the upper byte (D ...
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... CYC IL (Max – 0.2V. IL REF (min.) within 200ms. During this time V < (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Ambient [14] Temperature 1.8 ± 0.1 V 0°C to +70°C 1. Min. Typ. Max. 1.7 1 ...
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... Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. /I and load capacitance shown in ( test loads and t less than t . CLZ CHZ CO CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 167 MHz 133 MHz Min. Max. Min. Max. 6.0 7.9 7.5 2.4 – 3.0 2.4 – ...
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... Document #: 38-05497 Rev. *A PRELIMINARY Test Conditions T = 25° MHz 1. 1.5V DDQ V = 0.75V REF V 0.75V R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Max. Unit [12] ALL INPUT PULSES 1.25V 0.75V Slew Rate = Page ...
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... In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram., Document #: 38-05497 Rev. *A PRELIMINARY WRITE READ WRITE CYC t KHKH D31 D50 D51 D60 Q00 Q01 Q20 t DOH t DOH CYC t CCQO t CQOH t CCQO CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 NOP WRITE NOP D61 t HD Q21 Q40 Q41 t CHZ t CQD DON’T CARE UNDEFINED Page ...
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... It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Page ...
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... Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Page ...
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... IDLE Note: 24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05497 Rev. *A PRELIMINARY [24] SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE- CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... Boundary Scan Register TAP Controller [9,12,25] Over the Operating Range Test Conditions = −2 −100 µ 2 100 µ GND ≤ V ≤ CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 0 Selection Circuitry Min. Max. 1.4 1.6 0.4 0.2 0.65V –0.3 0.35V DD −5 5 Page TDO Unit ...
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... CS CH 27. Test conditions are specified using the load in TAP AC test conditions. t Document #: 38-05497 Rev. *A PRELIMINARY [26, 27] Over the Operating Range Description [27] 1. TMSS t TMSH t TDIS t TDIH t TDOV / ns CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Min. Max. Unit 100 ns 10 MHz ALL INPUT PULSES 0.9V ...
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... Bit Size 107 Description Boundary Scan Order Bump ID Bit # 11P 10P 10N 9P 10M 11N CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 CY7C1314AV18 512K x 36 Description 000 Version number. 00000110100 Allows unique identification of SRAM vendor. 1 Indicates the presence register. (continued) Bump 11L 18 11M 10L 21 ...
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... Boundary Scan Order (continued) Bit # Document #: 38-05497 Rev. *A PRELIMINARY Boundary Scan Order Bump ID Bit # 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 100 5B 101 5A 102 4A 103 5C 104 4B 105 3A 106 CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 (continued) Bump Page ...
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... CY7C1312AV18-167BZC CY7C1314AV18-167BZC 133 CY7C1310AV18-133BZC CY7C1312AV18-133BZC CY7C1314AV18-133BZC Package Diagram QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders. ...
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... Document History Page Document Title: CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 18-Mb QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05497 REV. ECN No. Issue Date ** 208405 see ECN *A 230396 see ECN Document #: 38-05497 Rev. *A PRELIMINARY Orig. of Change Description of Change DIM New Data Sheet VBL Upload datasheet to the internet ...