CY7C1312AV18-133BZC Cypress Semiconductor Corp, CY7C1312AV18-133BZC Datasheet - Page 10

• Manufacturer Part Number: CY7C1312AV18-133BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1312AV18-133BZC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Document #: 38-05497 Rev. *A
Switching Characteristics
Thermal Resistance
t
t
t
t
t
Set-up Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
Notes:
Parameter
16. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequncy,
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
18. t
19. At any given voltage and temperature t
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
Parameter
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
pulse levels of 0.25V to 1.25V, and output loading of the specified I
CHZ
Θ
Θ
, t
JA
JC
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
SA
SC
SC
SD
HA
HC
HC
HD
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHZ
CLZ
KC Var
KC lock
KC Reset
Parameter
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Description
[20]
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising
edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Set-up to K Clock Rise
Control Set-up to Clock (K, K) Rise (RPS, WPS)
Double Data Rate Control Set-up to Clock (K, K) Rise
(BWS
D
Address Hold after Clock (K and K) Rise
Control Hold after Clock (K and K) Rise (RPS, WPS)
Double Data Rate Control Hold after Clock (K and K) Rise
(BWS
D
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to
Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C and C) Rise to High-Z (Active to High-Z)
Clock (C and C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
[X:0]
[X:0]
0
Set-up to Clock (K and K) Rise
0
Hold after Clock (K and K) Rise
CHZ
, BWS
, BWS
Over the Operating Range
is less than t
Test conditions follow standard test methods and
procedures for measuring thermal impedence, per
EIA / JESD51.
1
1
, BWS
, BWS
CLZ
3
3
, BWS
, BWS
and t
Description
PRELIMINARY
CHZ
Test Conditions
OL
4
4
)
)
/I
less than t
[18,19]
OH
and load capacitance shown in (a) of AC test loads.
[16,17]
CO
.
[18,19]
–0.50
–0.40
–0.50
–0.50
1024
Min.
6.0
2.4
2.4
2.7
0.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
30
167 MHz
–
–
–
–
–
165 FBGAPackage
Max.
0.50
0.50
0.40
0.50
0.20
7.9
2.8
16.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.5
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
–0.50
–0.50
–0.40
–0.50
1024
Min.
3.38
7.5
3.0
3.0
0.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
30
–
–
–
–
–
133 MHz
DDQ
Page 10 of 21
Max.
3.55
0.50
0.50
0.40
0.50
0.20
8.4
= 1.5V, input
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-
°C/W
°C/W
Unit
Unit
cycl
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
es
ns