CY7C1327B-166AC Cypress Semiconductor Corp, CY7C1327B-166AC Datasheet
CY7C1327B-166AC
Specifications of CY7C1327B-166AC
Related parts for CY7C1327B-166AC
CY7C1327B-166AC Summary of contents
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... PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation Document #: 38-05140 Rev. ** The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when V and PowerPC™ All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Pin Configurations DDQ DDQ BYTE1 DDQ DDQ Document #: 38-05140 Rev. ** 7C1327-166 3.5 Commercial 420 Commercial 10 100-Lead TQFP CY7C1327B CY7C1327B 7C1327-133 7C1327-100 4.0 5.5 375 325 DDQ DDQ BYTE0 DDQ DDQ Page ...
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... DDQ ADV DDQ CLK BWE DDQ DQP MODE DDQ Description to select/deselect the device. ADSP is ignored select/deselect the device. to select/deselect the device. are also loaded into the burst counter. When ADSP and [1:0] CY7C1327B DDQ DQP DDQ DDQ DDQ DDQ , CE , and CE are sampled active. A ...
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... Max- imum access delay from the clock rise (t device). The CY7C1327B supports secondary cache in systems utiliz- ing either a linear or interleaved burst sequence. The inter- leaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... Because the CY7C1327B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ and DP inputs. Doing so will three-state the [15:0] [1:0] output drivers safety precaution, DQ automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ...
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... Write is defined by BWE and GW. See Write Cycle Description table. [1:0] 3. The DQ pins are controlled by the current cycle and the OE signal asynchronous and is not sampled with the clock. Document #: 38-05140 Rev ADSP CY7C1327B ADSC ADV ...
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... Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA 65°C to +150°C Operating Range 55°C to +125°C 0.5V to +4.6V Range Com’l 0. 0. 0.5V Industrial –40°C to +85°C DD ;DP = data when OE is active. [15:0] [1:0] CY7C1327B ...
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... V – 0. DDQ 7.5-ns cycle, 133 MHz 1/t MAX CYC 10-ns cycle, 100 MHz Max Device Deselected Test Conditions MHz 3.3V 3.3V DDQ CY7C1327B Min. Max. Unit 3.135 3.6 V 2.375 3.6 V 2.4 V 2.0 V 0.4 V 0 –0.3 0.8 V –0.3 0.7 ...
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... EOLZ CHZ CLZ CY7C1327B [10] ALL INPUT PULSES 2.5V 90% 90% 10% GND 2.5 ns (c) -133 -100 Min. Max. Min. Max. 7.5 10 1.9 3.5 1.9 3.5 2 ...
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... GW to define a write cycle (see Write Cycle Description table). [1:0] 15. WDx stands for Write Data to Address X. Document #: 38-05140 Rev. ** Burst Write ADSP ignored with WD2 masks ADSP UNDEFINED = DON’T CARE CY7C1327B Pipelined Write Unselected inactive ADSC initiated write WD3 Unselected with CE 2 High Page ...
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... Note: 16. RDx stands for Read Data from Address X. Document #: 38-05140 Rev. ** Burst Read ADSP ignored with Suspend Burst ADH OEHZ t DOH CLZ = DON’T CARE = UNDEFINED CY7C1327B Unselected Pipelined Read inactive 1 ADSC initiated read RD3 masks ADSP Unselected with CHZ 2 Page ...
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... Data bus is driven by SRAM, but data is not guaranteed. Document #: 38-05140 Rev. ** Single Write Burst Read ADSP ignored with ADH RD3 masks ADSP EOHZ t DS See Note Out In = DON’T CARE = UNDEFINED CY7C1327B Unselected Pipelined Read inactive DOH Out Out Out Out t CHZ Page ...
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... CE is the combination of CE and CE . All chip selects need to be active in order to select the device Document #: 38-05140 Rev CYC CH WD1 t ADH t WES ADSP ignored with CE HIGH Out Out In = DON’T CARE = UNDEFINED CY7C1327B t CL WD2 WD3 WD4 t CEH t WEH D( DOH t CHZ Page ...
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... I/Os Notes: 20. Device must be deselected when entering “ZZ” mode. See Cycle Description table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting “ZZ” sleep mode. Document #: 38-05140 Rev ZZS I (active DDZZ Three-state CY7C1327B t ZZREC Page ...
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... Ordering Information Speed (MHz) Ordering Code 166 CY7C1327B-166AC CY7C1327B-166BGC 133 CY7C1327B-133AC CY7C1327B-133BGC CY7C1327B-133AI CY7C1327B-133BGI 100 CY7C1327B-100AC CY7C1327B-100BGC CY7C1327B-100AI CY7C1327B-100BGI Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05140 Rev. ** Package Name Package Type A101 100-Lead Thin Quad Flat Pack ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1327B 51-85115 Page ...
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... Document Title: CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Document Number: 38-05140 Issue REV. ECN NO. Date ** 109884 09/10/01 Document #: 38-05140 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00935 to 38-05140 CY7C1327B Page ...