CY7C1327B-166AC Cypress Semiconductor Corp, CY7C1327B-166AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1327B-166AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1327B-166AC

• Density: 4Mb
• Access Time (max): 3.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 420mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

Because the CY7C1327B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
output drivers. As a safety precaution, DQ
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1327B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
output drivers. As a safety precaution, DQ
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1327B provides a two-bit wraparound counter, fed
by A
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ZZ Mode Electrical Characteristics
Document #: 38-05140 Rev. **
I
t
t
[17:0]
DDZZ
ZZS
ZZREC
[1:0]
Parameter
is loaded into the address register and the address ad-
, that implements either an interleaved or linear burst
[15:0]
[15:0]
and DP
and DP
[1:0]
) are asserted active to conduct a write to
[1:0]
[1:0]
Device operation to
ZZ recovery time
standby current
Snooze mode
Description
1
inputs. Doing so will three-state the
inputs. Doing so will three-state the
, CE
ZZ
2
, CE
[15:0]
3
are all asserted active,
and DP
[15:0]
[15:0]
Test Conditions
ZZ > V
ZZ > V
and DP
and DP
ZZ < 0.2V
[1:0]
DD
DD
is written
[1:0]
[1:0]
0.2V
0.2V
are
are
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
Linear Burst Sequence
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE
duration of t
A
00
01
10
11
A
00
01
10
11
[1:0]
[1:0]
Address
Address
1
, CE
First
First
2t
Min.
CYC
2
, CE
ZZREC
3
, ADSP, and ADSC must remain inactive for the
A
01
00
11
10
A
01
10
11
00
[1:0]
[1:0]
Address
Address
after the ZZ input returns LOW.
Second
Second
2t
Max.
CYC
3
A
10
11
00
01
A
10
11
00
01
[1:0]
[1:0]
Address
Address
Third
Third
CY7C1327B
A
11
10
01
00
A
11
00
01
10
Page 5 of 17
[1:0]
[1:0]
Unit
mA
Address
Address
ns
ns
Fourth
Fourth