CY7C1340A-100AC Cypress Semiconductor Corp, CY7C1340A-100AC Datasheet
CY7C1340A-100AC
Specifications of CY7C1340A-100AC
Related parts for CY7C1340A-100AC
CY7C1340A-100AC Summary of contents
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... Each memory cell consists of four transistors and two high valued resistors. The CY7C1340A/GVT71128C32 SRAM integrates 131,072 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
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... The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05153 Rev. *C BYTE 1 WRITE D Q BYTE 2 WRITE D Q BYTE 3 WRITE D Q BYTE 4 WRITE D Q ENABLE Input Register Address Register CLR Binary Counter & Logic CY7C1340A OUTPUT REGISTER DQ1 DQ32 Page ...
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... CLK. Global Write: This active LOW input allows a full 32-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. CY7C1340A NC 80 ...
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... No Connect: These signals are not internally connected. ) Burst Address Table (MODE = GND) CC Fourth First Address Address (internal) (external) A...A11 A...A00 A...A10 A...A01 A...A01 A...A10 A...A00 A...A11 CY7C1340A Description . CC Second Third Address Address (internal) (internal) A...A01 A...A10 A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 ...
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... Document #: 38-05153 Rev. *C Used CE CE2 CE2 ADSP None None None None None Next Next Next Next Next Next BWE BW1 CY7C1340A ADSC ADV WRITE OE CLK BW2 BW3 L–H High-Z L–H High-Z L–H High-Z L–H High-Z L–H High-Z L–H Q L–H High-Z L– ...
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... Max.; CLK frequency = 0 CC Device deselected; all inputs < Max.; CLK cycle time > Description Test Conditions T = 25° MHz 3.3V CC Description CY7C1340A Ambient [9] Temperature 3.3V −5%/+10% 0°C to +70°C –40°C to +85°C Min. Max. 2.0 V CCQ 2.0 4.6 –0.3 0.8 – ...
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... Description [23, 24] [23, 24] [25] [23, 24] [23, 24] [26] [26] is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1340A TQFP Typ 200us 90% Vddtyp 10% Vddm in ≤ 1.5 ns (c) (d) ALL INPUT PULSES 2.5V 90% 10% 0V ≤ ( 100 MHz 66 MHz Min ...
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... BW3#, BW4#, BWE#, GW# CE# ADV# OE# DQ Note: 27. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. Document #: 38-05153 Rev OEQ t OELZ KQLZ Q(A1) Q(A2) SINGLE READ CY7C1340A Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) BURST READ Q(A2+1) Page ...
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... Switching Waveforms (continued) [27] Write Timing CLK t S ADSP# ADSC ADDRESS A1 BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# ADV# OE# t KQX DQ Q Document #: 38-05153 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) SINGLE WRITE BURST WRITE CY7C1340A D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE D(A3+2) Page ...
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... ADSP# ADSC ADDRESS A2 BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# ADV# OE# DQ Ordering Information Speed (MHz) Ordering Code 100 CY7C1340A-100AC 66 CY7C1340A-66AI Document #: 38-05153 Rev Q(A1) Q(A2) D(A3) Single Reads Single Write Package Name A101 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack A101 100-lead 14 × ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1340A 51-85050-*A ...
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... Document History Page Document Title: CY7C1340A 128K × 32 Synchronous-Pipelined RAM Document Number: 38-05153 REV. ECN NO. Issue Date ** 109897 09/22/01 *A 111530 02/06/02 *B 123139 01/19/03 *C 212291 See ECN Document #: 38-05153 Rev. *C Orig. of Change SZV Changed from Spec number: 38-01003 to 38-05153 GLC Added industrial temp to data sheet RBI Added power up requirements to operating conditions information ...