CY7C1340A-100AC Cypress Semiconductor Corp, CY7C1340A-100AC Datasheet - Page 4

• Manufacturer Part Number: CY7C1340A-100AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1340A-100AC

• Density: 4Mb
• Access Time (max): 5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 225mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 32b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05153 Rev. *C
Pin Descriptions
Burst Address Table (MODE = NC/V
(external)
MODE
ADSC
Address
Name
ADSP
DQ1–
DQ32
V
V
ADV
A...A00
A...A01
A...A10
A...A11
CLK
CE2
CE2
V
V
CE
OE
NC
ZZ
CCQ
SSQ
First
CC
SS
Asynchronous
(internal)
Address
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Second
A...A01
A...A00
A...A11
A...A10
I/O Ground
I/O Supply
Ground
Supply
Output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Input/
Type
Input
-
(internal)
Address
A...A10
A...A00
A...A01
A...A11
Third
Clock: This signal registers the addresses, data, chip enables, Write control and burst
control inputs on its rising edge. All synchronous inputs must meet set-up and hold times
around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to gate ADSP.
Chip Enable: This active LOW input is used to enable the device.
Chip Enable: This active HIGH input is used to enable the device.
Output Enable: This active LOW asynchronous input enables the data output drivers.
Address Advance: This active LOW input is used to control the internal burst counter.
A HIGH on this pin generates wait cycle (no address advance).
Address Status Processor: This active LOW input, along with CE being LOW, causes a
new external address to be registered and a Read cycle is initiated using the new address.
Address Status Controller: This active LOW input causes device to be de-selected or
selected along with new external address to be registered. A Read or Write cycle is initiated
depending upon Write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC
or HIGH on this pin selects Interleaved Burst.
Snooze: This active HIGH input puts the device in low power consumption standby mode.
For normal operation, this input has to be either LOW or NC (No Connect).
Data Inputs/Outputs: First Byte is DQ1–DQ8. Second Byte is DQ9–DQ16. Third Byte is
DQ17–DQ24. Fourth Byte is DQ25–DQ32. Input data must meet set-up and hold times
around the rising edge of CLK.
Power Supply: +3.3V –5% to +10%. Pin 14 does not have to be connected directly to
V
Ground: GND
Output Buffer Supply: +3.3V –5% to +10%. For 2.5V I/O: 2.375V to V
Output Buffer Ground: GND
No Connect: These signals are not internally connected.
CC
as long as it is greater than V
CC
(internal)
Address
)
A...A10
A...A01
A...A00
Fourth
A...A11
Burst Address Table (MODE = GND)
(external)
Address
A...A00
A...A01
A...A10
A...A11
First
IH
.
Description
(internal)
Address
Second
A...A01
A...A10
A...A11
A...A00
(internal)
Address
A...A10
A...A00
A...A01
A...A11
Third
CY7C1340A
CC
.
Page 4 of 12
(internal)
Address
A...A00
A...A01
A...A10
Fourth
A...A11