CY7C1354A-166AC Cypress Semiconductor Corp, CY7C1354A-166AC Datasheet

CY7C1354A-166AC

Manufacturer Part Number

CY7C1354A-166AC

Description

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1354A-166AC.pdf (31 pages)

2.CY7C1354A-166AC.pdf (28 pages)

3.CY7C1354A-166AC.pdf (28 pages)

4.CY7C1354A-166AC.pdf (31 pages)

Specifications of CY7C1354A-166AC

Density

9Mb

Access Time (max)

3.6ns

Operating Supply Voltage (typ)

3.3V

Package Type

TQFP

Operating Temp Range

0C to 70C

Supply Current

480mA

Operating Supply Voltage (min)

3.14V

Operating Supply Voltage (max)

3.47V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Lead Free Status / Rohs Status

Not Compliant

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Cypress Semiconductor Corporation

Document #: 38-05161 Rev. *B

Features

Functional Description

The

GVT71512ZC18 SRAMs are designed to eliminate dead

cycles when transitioning from Read to Write or vice versa.

These SRAMs are optimized for 100% bus utilization and

achieve Zero Bus Latency

(NoBL ). They integrate 262,144 × 36 and 524,288 × 18

SRAM cells, respectively, with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. These employ high-speed, low-power CMOS

designs using advanced triple-layer polysilicon, double-layer

metal technology. Each memory cell consists of four

transistors and two high-valued resistors.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current Commercial

• Zero Bus Latency, no dead cycles between Write and

• Fast clock speed: 200, 166, 133, 100 MHz

• Fast access time: 3.2, 3.6, 4.2, 5.0 ns

• Internally synchronized registered outputs eliminate

• Single 3.3V –5% and +5% power supply V

• Separate V

• Single WEN (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

• Interleaved or linear four-word burst capability

• Individual byte Write (BWa–BWd) control (may be tied

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

•Automatic power-down feature available using ZZ mode

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid

Read cycles

the need to control OE

control signal registers for fully pipelined applications

LOW)

or CE select

Array), and 100-pin TQFP packages

CY7C1354A/GVT71256ZC36

CCQ

for 3.3V or 2.5V I/O

(ZBL )/No Bus Latency

Commercial

and

•

3901 North First Street

CY7C1356A/

256K x 36/512K x 18 Pipelined SRAM

7C1354A-200

7C1356A-200

71256ZC36-5

71512ZC18-5

560

3.2

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE, CE

Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,

and BWd), and Read-Write Control (WEN). BWc and BWd

apply to CY7C1354A/GVT71256ZC36 only.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either Read or Write.

A clock enable (CEN) pin allows operation of the

CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18

to be suspended as long as necessary. All synchronous inputs

are ignored when (CEN) is HIGH and the internal device

registers will hold their previous values.

There are three chip enable pins (CE, CE

user to deselect the device when desired. If any one of these

three are not active when ADV/LD is LOW, no new memory

operation can be initiated and any burst cycle in progress is

stopped. However, any pending data transfers (Read or Write)

will be completed. The data bus will be in high-impedance

state two cycles after chip is deselected or a Write cycle is

initiated.

The

GVT71512ZC18 have an on-chip two-bit burst counter. In the

burst

CY7C1356A/GVT71512ZC18 provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the MODE input pin. The MODE pin

selects between linear and interleaved burst sequence. The

ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH)

Output Enable (OE), Sleep Enable (ZZ) and burst sequence

select (MODE) are the asynchronous signals. OE can be used

to disable the outputs at any given time. ZZ may be tied to

LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

7C1354A-166

7C1356A-166

71256ZC36-6

71512ZC18-6

CY7C1354A/GVT71256ZC36

•

mode,

480

3.6

with NoBL™ Architecture

San Jose

CY7C1354A/GVT71256ZC36

CY7C1356A/GVT71512ZC18

the

71256ZC36-7.5

71512ZC18-7.5

7C1354A-133

7C1356A-133

, and CE

CY7C1354A/GVT71256ZC36

•

410

4.2

CA 95134

), Cycle Start Input (ADV/LD),

Revised April 25, 2002

71256ZC36-10

71512ZC18-10

7C1354A-100

7C1356A-100

and

, CE

•

350

5.0

408-943-2600

) that allow the

CY7C1356A/

Unit

and

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