CY7C1354A-200AC Cypress Semiconductor Corp, CY7C1354A-200AC Datasheet
CY7C1354A-200AC
Specifications of CY7C1354A-200AC
Related parts for CY7C1354A-200AC
CY7C1354A-200AC Summary of contents
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... Write cycle is initiated. The CY7C1354A and CY7C1356A have an on-chip two-bit burst counter. In the burst mode, the CY7C1354A and CY7C1356A provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin ...
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... Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05161Rev. *E [1] Input Registers 3 [1] Input Registers CY7C1354A CY7C1356A Address Control Control Logic Sel Mux Output Registers Output Buffers DQa-DQd ...
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... DQb DQa 18 63 DQa DQb CCQ 20 61 CCQ DQa DQb 22 59 DQa DQb 23 58 DQa DPb 24 57 DQa CCQ 27 54 CCQ DQa DQa DQa CY7C1354A CY7C1356A DQa 74 DQa 73 DQa DQa 69 DQa 68 CY7C1356A (512K × 18 DQa 63 DQa DQa 59 DQa Page CCQ SS SS ...
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... DQd M V CCQ N DQd P DQd CCQ Table CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb CCQ Document #: 38-05161Rev. *E 119-ball Bump BGA CY7C1354A (256K × 36)–7 × 17 BGA ADV/ DQc DQc DQc DQc BWc A BWb DQc V WEN DQd V CLK V SS ...
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... ADV/ Read or Write operation. The data bus activity for the current cycle takes place two clock cycles later. Input- Clock: This is the clock input to CY7C1354A. Except for OE, ZZ and Synchronous MODE, all timing references for the device are made with respect to the rising edge of CLK ...
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... The effect of CEN sampled HIGH on the device outputs the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. CY7C1354A CY7C1356A Pin Description . or to GND. ...
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... Power Supply: +3.3V –5% and +5%. CC Ground Ground: GND. SS I/O Supply Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V –0.125V and +0.4V for 2.5V I/O. CY7C1354A CY7C1356A Pin Description 3 sampled HIGH used with CE and CE 2 has inverted polarity but otherwise is identical to 2 ...
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... No Connect: These signals are not internally connected. It can be left floating or be connected to V [2] WEN Linear Burst Address Table (MODE = V Fourth First Address Address [5] (internal) (external) A...A A... A...A A... A...A A... A...A A... CY7C1354A CY7C1356A Pin Description or to GND. CC [4] BWa BWb BWc Second Third Address Address (internal) (internal) A...A A...A ...
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... Read Next X X External H Read Next X X External L Write Next X X External L Write Next are all True. HIGH means are HIGH CY7C1354A CY7C1356A after the ZZ input returns LOW. CEN needs to active Min. Max. – 0. – 0. CYC ZZ < 0.2V 2t CYC CE CEN BWx ...
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... The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number. CY7C1354A CY7C1356A ) CC ) ...
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... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. CY7C1354A CY7C1356A 1149.1-mandatory plus t ). The CS CH ...
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... The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05161Rev. *E SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1354A CY7C1356A 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [21] Page ...
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... I OHC [23 8.0 mA OLT [23 8.0 mA OHT /2; undershoot: V (AC) <–0.5V for t < t /2; power-up KHKH . Control input signals (such as WEN and ADV/LD) may not have pulse widths less than t CC CY7C1354A CY7C1356A 0 Selection Circuitry [22] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 – ...
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... CS CH 27. Test conditions are specified using the load in TAP AC test conditions. Document #: 38-05161Rev. *E [26, 27] Over the Operating Range Description CY7C1354A CY7C1356A Min. Max. Unit MHz 8 ns ...
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... XXXXXX XXXXXX 00011100100 00011100100 1 1 Bit Size (x18 CY7C1354A CY7C1356A ALL INPUT PULSES 3.0V 1.5V 1 TLTH Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. ...
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... Bump ID Bit CY7C1354A CY7C1356A Description (continued) Signal Name TQFP Bump ADV/ CEN 87 4M WEN 88 4H CLK BWa 93 BWb 94 5G BWc 95 3G BWd 100 2A DQc 1 2D DQc 2 1E DQc 3 DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 2E DQc 12 2G DQc DQd 18 2K ...
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... WEN 27 CLK Document #: 38-05161Rev. *E Boundary Scan Order (512K × 18) (continued) Bump ID Bit Bump CY7C1354A CY7C1356A (continued) Signal Name TQFP Bump BWa 93 BWb 100 2A DQb 8 1D DQb 9 2E DQb 12 2G DQb DQb 18 2K DQb 19 DQb 22 2M DQb 23 1N DQb 24 2P MODE Page ...
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... Device deselected; all inputs < > MAX CLK cycle time > t Min. KC < –2.0V for t < means no input lines are changing. CYC CY7C1354A CY7C1356A Ambient [28] [29,30] Temperature V CC 3.3V ± 5% 0°C to +70°C –40°C to +85°C Min. Max. 2 2.0 1.7 – ...
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... KQHZ KQLZ OEHZ CY7C1354A CY7C1356A Typ. Max 6.5 TQFP Typ 200us Vcctyp 90% Vccmin For proper RESET bring Vcc down to 0V 10% ≤ 1.0 ns (d) -6/ -7 ...
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... etc., where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state 2 is HIGH. 2 CY7C1354A CY7C1356A (Burst Wraps around (CKE# HIGH , eliminates to initial state) current L-H clock edge) Q(A ...
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... D(A + Pipeline Write ) represents the first input to the external address etc., where address bits A0 and A1 are advancing for the four-word burst in the sequence defined by the state of the CY7C1354A CY7C1356A (CKE# HIGH , eliminates (Burst Wraps around current L-H clock edge) D(A ...
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... KQ DATA Out (Q) Read DATA In (D) Note: 48. Q(A ) represents the first output from the external address A 1 Document #: 38-05161Rev BW KQHZ KQLZ Q Read D Write . D(A ) represents the input data to the SRAM corresponding to address CY7C1354A CY7C1356A KQX Q Read D Write Q Page ...
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... CEN when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous states. Document #: 38-05161Rev KQHZ Q KQLZ CY7C1354A CY7C1356A KQX D Page Q ...
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... When either one of the Chip Enables (CE, CE cycle after t Document #: 38-05161Rev KQHZ Q KQX D(A ) represents the input data to the SRAM corresponding to address sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one 2 3 CY7C1354A CY7C1356A OEHZ Q D etc. 3 Page ...
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... ZZ Mode Timing CLK CE 1 LOW CE 2 HIGH I/Os Ordering Information Speed (MHz) Ordering Code [52] 200 CY7C1354A-200AC CY7C1354A-200BGC [52] 166 CY7C1354A-166AC CY7C1354A-166BGC CY7C1356A-166AC 133 CY7C1354A-133BGC CY7C1356A-133AC 100 CY7C1356A-100AC CY7C1356A-100BGC Speed (MHz) Ordering Code [52] 166 CY7C1354A-166BGI 133 CY7C1354A-133BGI CY7C1356A-133AI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...
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... Package Diagrams 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05161Rev. *E CY7C1354A CY7C1356A 51-85050-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead PBGA ( 2.4 mm) BG119 CY7C1354A CY7C1356A 51-85115-*B ...
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... Document History Page Document Title: CY7C1354A/CY7C1356A 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05161 REV. ECN No. Issue Date ** 3000 4/21/00 *A 114095 03/12/02 *B 114095 05/30/02 *C 121473 11/14/02 *D 123143 01/18/03 *E 216628 03/24/04 Document #: 38-05161Rev. *E Orig. of Change Description of Change CXV ...