CY7C1354B-166BZC Cypress Semiconductor Corp, CY7C1354B-166BZC Datasheet - Page 29

• Manufacturer Part Number: CY7C1354B-166BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354B-166BZC

• Density: 9Mb
• Access Time (max): 3.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05114 Rev. *C
Document History Page
Document Title: CY7C1354B/CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM
NoBL™ Architecture
Document Number: 38-05114
REV.
*C
*A
*B
**
ECN No.
126207
205060
230388
117904
Issue Date
See ECN
See ECN
08/28/02
08/27/03
Change
Orig. of
DPM
RCS
NJY
VBL
New Data Sheet
Removed Preliminary status
Removed 250-MHz Speed bin
Added 225-MHz speed bin
Increased T
Updated JTAG revision number and device depth
Updated JTAG boundary scan orders
Added t
Changed footnotes ordering
Added Industrial operating range
Changed Capacitance table to have TQFP, BGA, and fBGA columns.
Removed footnote 13 “
Removed footnote 14 “
Changed footnote 15 from “
V
200 ms.
undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
Added footnote 14 “
During this time V
Added footnote 20 “
V
Changed footnote 21 from “
“
Updated ZZ Mode Electrical Characteristics.
Updated I
Modified functional block diagram.
Modified Truth Table and Write Cycle Descriptions.
Updated Ordering Information.
Modified ID code
Changed balls B4 and A5 from BW
to BW
Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11
from DQb to DQa for CY7C1356B.
Update Ordering Info section: changed BZC to BZI in Industrial part
Test conditions shown in (a) of AC Test Loads unless otherwise noted.
IL
DDQ
(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
= 2.5V.”
b
“to footnote 13“
Power
for 165-ball FBGA package for CY7C1356B
SB1
CO
specification
IH
and I
, T
< V
EOV
DD
SB3
T
Timing reference level is 1.5V when V
and V
, T
Power-up
Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2),
Minimum voltage equals –2.0V for pulse durations of less than 20 ns.”
TA is the case temperature.”
currents in Electrical Characteristics table.
CHZ
DDQ
Description of Change
: Assumes a linear ramp from 0V to V
, T
Test conditions shown in (a), (b) and (c) of AC Test Loads.
Overshoot: V
< V
EOHZ
DD
.
“
d
for 200 MHz to 3.2 ns from 3.0 ns
and BW
IH
(AC) < V
b
DD
“
to NC and ball A4 from BW
+ 1.5V for t < t
DDQ
= 3.3V and is 1.25V when
CY7C1356B
CY7C1354B
“
DD
(min.) within 200ms.
TCYC
Page 29 of 29
/2; undershoot:
with
“to
c
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