CY7C1354B-166BZC Cypress Semiconductor Corp, CY7C1354B-166BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1354B-166BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354B-166BZC

• Density: 9Mb
• Access Time (max): 3.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05114 Rev. *C
Truth Table
Deselect Cycle
Continue
Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy
Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/WRITE
ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE
CLOCK EDGE
(Stall)
Sleep MODE
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQs = data when OE is active.
Operation
[1, 2, 3, 4, 5, 6, 7]
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
Address
Used
[a:d]
. See Write Cycle Description table for details.
CE ZZ
H
X
X
X
X
X
X
X
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
ADV/LD
H
H
H
H
H
X
X
L
L
L
L
L
WE BWx
X
X
H
X
H
X
X
X
X
X
L
L
X
X
X
X
X
X
H
H
X
X
L
L
X
X
L
L
H
H
X
X
X
X
X
X
OE
L
L
L
L
L
L
L
L
L
H
X
L
CEN CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
Data In (D)
Data In (D)
DQ
CY7C1356B
CY7C1354B
-
[a:d]
= Three-state when
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