CY7C1355B-133AC Cypress Semiconductor Corp, CY7C1355B-133AC Datasheet
CY7C1355B-133AC
Specifications of CY7C1355B-133AC
Related parts for CY7C1355B-133AC
CY7C1355B-133AC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05117 Rev. *C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Functional Description The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the CY7C1355B/CY7C1357B is equipped with the advanced No ...
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... Logic Block Diagram – CY7C1355B (256K x 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ ADDRESS A0, A1 REGISTER BW D MODE WE CE CLK C CEN OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL ADV/ Logic Block Diagram – CY7C1357B (512K x 18) ADDRESS A0, A1, A ...
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... Pin Configurations DQP DDQ BYTE DDQ DNU DDQ BYTE DDQ DQP 30 D Document #: 38-05117 Rev. *C 100-lead TQFP CY7C1355B CY7C1355B CY7C1357B 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page [+] Feedback ...
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... Pin Configurations (continued DDQ DDQ DNU BYTE DDQ DQP DDQ Document #: 38-05117 Rev. *C 100-lead TQFP CY7C1357B CY7C1355B CY7C1357B DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...
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... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ 72M U V DDQ Document #: 38-05117 Rev. *C 119-ball BGA (3 Chip Enables with JTAG) CY7C1355B (256K x 36 18M ADV/ DQP CLK CEN DQP MODE 72M TMS TDI TCK TDO CY7C1357B (512K x 18) ...
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... DDQ N DQP DDQ 72M A R MODE NC / 36M 288M CE2 DDQ DDQ DDQ DDQ DDQ / DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05117 Rev. *C 165-ball fBGA (3 Chip enable with JTAG) CY7C1355B (256K x 36 CEN CLK TDI A1 TDO A A0 ...
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... CY7C1355B–Pin Definitions Name TQFP BGA 37,36,32,33, P4,N4,A2 34,35,44,45, C2,R2,A3, A9,A10,B2, 46,47,48,49, B3,C3,T3, B10,P3,P4, 50,81,82,83, G4,T4,A5, P8,P9,P10, 99,100 B5,C5,T5, R3,R4,R8, A6,C6,R6 R9,R10,R11 93,94,95,96 L5,G5,G3 ADV/LD CLK CEN Document #: 38-05117 Rev. *C fBGA I/O R6,P6,A2, Input- Address Inputs used to select one of the 256K Synchronous address locations ...
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... CY7C1355B–Pin Definitions (continued) Name TQFP BGA 52,53,56,57, K6,L6,M6 58,59,62,63, N6,K7,L7, 68,69,72,73, N7,P7,E6, 74,75,78,79, F6,G6,H6, 2,3,6,7,8,9, D7,E7,G7, 12,13,18,19, H7,D1,E1, 22,23,24,25, G1,H1,E2, 28,29 F2,G2,H2, K1,L1,N1, P1,K2,L2, G1,D2,E2, M2,N2 51,80,1,30 P6,D6,D2, N11,C11,C1, DQP [A:D] P2 MODE 15,41,65,91 J2,C4,J4, D4,D8,E4, DD R4,J6 G4,G8,H2, V 4,11,20,27, A1,F1,J1, C3,C9,D3, ...
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... CY7C1355B–Pin Definitions (continued) Name TQFP BGA TCK - U4 NC 16,38,39,42, B1,C1,R1, A1,A11,B1, 43,66,84 T1,T2,J3, B9,B11,C2, A4,D4,L4, C10,H1,H3, J5,R5,T6, H9,H10,N2, U6,B7,C7, N5,N6,N7, R7 N10,P1,P2, V /DNU CY7C1357B–Pin Definitions Name TQFP BGA 37,36,32,33, P4,N4,A2, R6,P6,A2 34,35,44,45, C2,R2,T2, A9,A10,A11, 46,47,48,49, A3,B3,C3, B2,B10,P3, 50,80,81,82, T3,A5,B5, P4,P8,P9, ...
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... Serial data-out to the JTAG circuit. Delivers data on the output negative edge of TCK. If the JTAG feature is not being Synchronous utilized, this pin should be left unconnected. This pin is not available on TQFP packages. CY7C1355B CY7C1357B Description are placed in a three-state condition. The . During Write sequences, s correspondingly ...
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... TQFP packages Connects. Not internally connected to the die. 18M,36M, 72M, 144M and 288M are address expansion pins and are not internally connected to the die. - Ground/DNU This pin can be connected to Ground or should be left floating. CY7C1355B CY7C1357B Description through a pull DD . This pin This SS ...
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... A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1355B/CY7C1357B is a common I device, data should not be driven into the device while the 1 2 outputs are active ...
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... data when OE is active. X CY7C1355B CY7C1357B Second Third Fourth Address Address Address A1: A0 A1 Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns CEN CLK L->H Three-State L->H Three-State L->H Three-State L->H Three-State L->H Data Out ( L->H Data Out ( L->H Three-State ...
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... Truth Table for Read/Write Function (CY7C1355B) Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C – (DQ and DQP ) C C Write Byte D – (DQ and DQP ) D D Write All Bytes [2, 3] Truth Table for Read/Write ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355B/CY7C1357B incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture set-up plus hold time (t plus The SRAM clock input might not be captured correctly if there portion way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1355B CY7C1357B Unlike the SAMPLE/PRELOAD Page [+] Feedback ...
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... These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [9, 10] Over the operating Range Description / ns CY7C1355B CY7C1357B TDOV Min. Max. Unit MHz ...
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... OL DDQ 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1355B CY7C1357B V to 2.5V SS 1.25V 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...
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... Reserved for Internal Use 000000 000000 Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor 1 1 Indicates the presence register Bit Size (x36 Description CY7C1355B CY7C1357B Description Bit Size (x18 Page [+] Feedback ...
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... BGA Boundary Scan Order CY7C1355B (256K x 36) BIT BALL Signal BIT BALL # ID Name # ID 1 CLK CEN ADV/ DQP Internal DQP Document #: 38-05117 Rev. *C CY7C1357B (512K x 18) Signal BIT# BALL ID Signal Name Name A 1 CLK CEN MODE 5 B4 ADV/LD DQP 6 G4 ...
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... Boundary Scan Order CY7C1355B (256K x 36) BIT# BALL Signal BIT# BALL ID Name 1 B6 CLK CEN ADV/ B10 A10 C11 DQP E10 F10 G10 D10 D11 E11 DQ 51 Internal B 16 F11 G11 H11 J10 K10 L10 M10 J11 K11 DQ 60 ...
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... All Speeds DD ≥ V ≤ 0.3V /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1355B CY7C1357B Ambient Temperature DDQ 0°C to +70°C 3.3V – 5%/+10% 2.5V – Min. Max. Unit 3.135 3.63 3.135 V DD 2.375 2 ...
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... MHz 3.3V 2.5V DDQ R = 317Ω 3.3V V OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2. OUTPUT GND =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1355B CY7C1357B BGA fBGA Package Package Unit °C °C BGA fBGA Package Package Unit ...
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... DDQ is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355B CY7C1357B 117 MHz 100 MHz Max. Min. Max. Unit ...
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... CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355B CY7C1357B OEV t CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) ...
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... Document #: 38-05117 Rev CDV t DOH t OEV t CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED CY7C1355B CY7C1357B CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) Page [+] Feedback ...
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... ZZ Mode Timing CLK ZZI I SUPPLY I DDZZ ALL INPUTS (except ZZ) Outputs (Q) Ordering Information 3 Speed (MHz) Ordering Code 133 CY7C1355B-133AC CY7C1357B-133AC CY7C1355B-133AI CY7C1357B-133AI CY7C1355B-133BGC CY7C1357B-133BGC CY7C1355B-133BGI CY7C1357B-133BGI CY7C1355B-133BZC CY7C1357B-133BZC CY7C1355B-133BZI CY7C1357B-133BZI 117 CY7C1355B-117AC CY7C1357B-117AC CY7C1355B-117AI CY7C1357B-117AI CY7C1355B-117BGC CY7C1357B-117BGC CY7C1355B-117BGI CY7C1357B-117BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. ...
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... CY7C1355B-117BZI CY7C1357B-117BZI 100 CY7C1355B-100AC CY7C1357B-100AC CY7C1355B-100AI CY7C1357B-100AI CY7C1355B-100BGC CY7C1357B-100BGC CY7C1355B-100BGI CY7C1357B-100BGI CY7C1355B-100BZC CY7C1357B-100BZC CY7C1355B-100BZI CY7C1357B-100BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05117 Rev. *C Package Name Part and Package Type BB165A 165-ball Fine-Pitch Ball Grid Array ( 1.2mm) ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05117 Rev. *C CY7C1355B CY7C1357B 51-85050-*A Page [+] Feedback ...
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... Package Diagrams (continued) 119-Lead PBGA ( 2.4 mm) BG119 Document #: 38-05117 Rev. *C CY7C1355B CY7C1357B 51-85115-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1355B CY7C1357B 51-85122-*C ...
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... Document History Page Document Title: CY7C1355B/CY7C1357B 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05117 REV. ECN NO. Issue Date ** 117908 08/28/02 *A 123161 12/18/02 *B 200980 See ECN *C 239272 See ECN Document #: 38-05117 Rev. *C Orig. of Change Description of Change RCS ...